C8051F040-TB Silicon Laboratories Inc, C8051F040-TB Datasheet - Page 297

• Manufacturer Part Number: C8051F040-TB
• Description: BOARD PROTOTYPING W/C8051F040
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040-TB

• Contents: Board
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F040
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F040/1/2/3/4/5/6/7
23.2. Timer 2, Timer 3, and Timer 4
Timers n are 16-bit counter/timers, each formed by two 8-bit SFRs: TMRnL (low byte) and TMRnH (high
byte) where n = 2, 3, and 4 for timers 2, 3, and 4 respectively. These timers feature auto-reload, capture,
and toggle output modes with the ability to count up or down. Capture Mode and Auto-reload mode are
selected using bits in the Timer n Control registers (TMRnCN). Toggle output mode is selected using the
Timer 2, 3, and 4 Configuration registers (TMRnCF). These timers may also be used to generate a square-
wave at an external pin. As with Timers 0 and 1, Timers n can use either the system clock (divided by one,
two, or twelve), external clock (divided by eight) or transitions on an external input pin as its clock source.
The Counter/Timer Select bit C/Tn (TMRnCN.1) configures the peripheral as a counter or timer. Clearing
C/Tn configures the Timer to be in a timer mode (i.e., the system clock or external clock as input for the
timer). When C/Tn is set to 1, the timer is configured as a counter (i.e., high-to-low transitions at the Tn
input pin increment (or decrement) the counter/timer register). Refer to
Section “17.1. Ports 0 through 3
and the Priority Crossbar Decoder” on page 204
for information on selecting and configuring external I/
O pins for digital peripherals, such as the Tn pin. Timer 2 and 3 can be used to start an ADC Data Conver-
sion and Timers 2, 3, and 4 can schedule DAC outputs. Only Timer 1 can be used to generate baud rates
for UART 1, and Timers 1, 2, 3, or 4 may be used to generate baud rates for UART 0.
Timer n can use either SYSCLK, SYSCLK divided by 2, SYSCLK divided by 12, an external clock divided
by 8, or high-to-low transitions on the Tn input pin as its clock source when operating in Counter/Timer with
Capture mode. Clearing the C/Tn bit (TMRnCN.1) selects the system clock/external clock as the input for
the timer. The Timer Clock Select bits TnM0 and TnM1 in TMRnCF can be used to select the system clock
undivided, system clock divided by two, system clock divided by 12, or an external clock provided at the
XTAL1/XTAL2 pins divided by 8 (see SFR Definition 23.9). When C/Tn is set to logic 1, a high-to-low tran-
sition at the Tn input pin increments the counter/timer register (i.e., configured as a counter).
23.2.1. Configuring Timer 2, 3, and 4 to Count Down
Timers 2, 3, and 4 have the ability to count down. When the timer’s respective Decrement Enable Bit
(DCEN) in the Timer Configuration Register (See SFR Definition 23.9) is set to ‘1’, the timer can then count
up or down. When DCEN = 1, the direction of the timer’s count is controlled by the TnEX pin’s logic level.
When TnEX = 1, the counter/timer will count up; when TnEX = 0, the counter/timer will count down. To use
this feature, TnEX must be enabled in the digital crossbar and configured as a digital input.
Note: When DCEN = 1, other functions of the TnEX input (i.e., capture and auto-reload) are not available.
TnEX will only control the direction of the timer when DCEN = 1.
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