C8051F040-TB Silicon Laboratories Inc, C8051F040-TB Datasheet - Page 270

BOARD PROTOTYPING W/C8051F040

C8051F040-TB

Manufacturer Part Number
C8051F040-TB
Description
BOARD PROTOTYPING W/C8051F040
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F040-TB

Contents
Board
Processor To Be Evaluated
C8051F04x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F040
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
C8051F040/1/2/3/4/5/6/7
21.1.4. Mode 3: 9-Bit UART, Variable Baud Rate
Mode 3 uses the Mode 2 transmission protocol with the Mode 1 baud rate generation. Mode 3 operation
transmits 11 bits: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The baud
rate is derived from Timer 1 or Timer 2, 3, or 4 overflows, as defined by Equation 21.1 and Equation 21.3.
Multiprocessor communications and hardware address recognition are supported, as described in
Section
21.2.
21.2. Multiprocessor Communications
Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave
processors by special use of the ninth data bit and the built-in UART0 address recognition hardware. When
a master processor wants to transmit to one or more slaves, it first sends an address byte to select the tar-
get(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is
always set to logic 0. UART0 will recognize as “valid” (i.e., capable of causing an interrupt) two types of
addresses: (1) a masked address and (2) a broadcast address at any given time. Both are described
below.
270
Rev. 1.5

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