EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 383
EVB9S08DZ60
Manufacturer Part Number
EVB9S08DZ60
Description
BOARD EVAL FOR 9S08DZ60
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(2 pages)
3.EVB9S08DZ60.pdf
(32 pages)
4.EVB9S08DZ60.pdf
(13 pages)
5.EVB9S08DZ60.pdf
(4 pages)
Specifications of EVB9S08DZ60
Contents
Module and Misc Hardware
Processor To Be Evaluated
S08D
Data Bus Width
8 bit
Interface Type
RS-232, USB
Silicon Manufacturer
Freescale
Core Architecture
HCS08
Core Sub-architecture
HCS08
Silicon Core Number
MC9S08
Silicon Family Name
S08D
Kit Contents
Board Cables CD Power Supply
Rohs Compliant
Yes
For Use With/related Products
MC9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EVB9S08DZ60
Manufacturer:
TI
Quantity:
101
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1
2
3
4
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
Freescale Semiconductor
Typical data was characterized at 5.0 V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of t
clock frequency changes to the untrimmed DCO frequency (freset = (f
reset to 0; and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value.
Timing is shown with respect to 20% V
Nu
m
1
2
3
4
5
6
7
8
D/
D
D
D
D
D
P
T
T
C
Control Timing
Bus frequency (t
Internal low-power oscillator period
External reset pulse width
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ/PIAx/ PIBx/PIDx pulse width
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Asynchronous path
Synchronous path
RESET PIN
Slew rate control disabled (PTxSE = 0)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
Slew rate control enabled (PTxSE = 1)
3
cyc
= 1/f
3
2
Rating
Bus
2
DD
)
MC9S08DZ60 Series Data Sheet, Rev. 4
and 80% V
Table A-13. Control Timing
Figure A-2. Reset Timing
DD
levels. Temperature range –40°C to 125°C.
4
4
t
extrst
t
t
t
dco_ut
Rise
Rise
Symbol
ILIH,
t
t
t
MSSU
t
t
rstdrv
f
extrst
MSH
LPO
Bus
, t
, t
t
IHIL
)/4) because TRIM is reset to 0x80 and FTRIM is
Fall
Fall
1.5 x t
34 x t
1.5 t
100
Min
dc
—
25
25
—
—
—
—
cyc
cyc
cyc
Appendix A Electrical Characteristics
cyc
Typical
. After POR reset, the bus
1500
40
75
11
35
—
—
1
Max
20
—
—
—
—
—
—
MHz
Unit
μs
ns
ns
ns
ns
ns
ns
ns
383
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