EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 275
EVB9S08DZ60
Manufacturer Part Number
EVB9S08DZ60
Description
BOARD EVAL FOR 9S08DZ60
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(2 pages)
3.EVB9S08DZ60.pdf
(32 pages)
4.EVB9S08DZ60.pdf
(13 pages)
5.EVB9S08DZ60.pdf
(4 pages)
Specifications of EVB9S08DZ60
Contents
Module and Misc Hardware
Processor To Be Evaluated
S08D
Data Bus Width
8 bit
Interface Type
RS-232, USB
Silicon Manufacturer
Freescale
Core Architecture
HCS08
Core Sub-architecture
HCS08
Silicon Core Number
MC9S08
Silicon Family Name
S08D
Kit Contents
Board Cables CD Power Supply
Rohs Compliant
Yes
For Use With/related Products
MC9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EVB9S08DZ60
Manufacturer:
TI
Quantity:
101
- DEMO9S08DZ60 PDF datasheet
- EVB9S08DZ60 PDF datasheet #2
- EVB9S08DZ60 PDF datasheet #3
- EVB9S08DZ60 PDF datasheet #4
- EVB9S08DZ60 PDF datasheet #5
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13.1.1
Features of the SPI module include:
13.1.2
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
13.1.2.1
Figure 13-2
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
Freescale Semiconductor
•
•
•
•
•
•
•
Master or slave mode operation
Full-duplex or single-wire bidirectional option
Programmable transmit bit rate
Double-buffered transmit and receive
Serial clock phase and polarity options
Slave select output
Selectable MSB-first or LSB-first shifting
7
6
Features
Block Diagrams
shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
SPI System Block Diagram
5
GENERATOR
SPI SHIFTER
MASTER
CLOCK
4
3
2
1
0
Figure 13-2. SPI System Connections
MC9S08DZ60 Series Data Sheet, Rev. 4
MOSI
MISO
SPSCK
SS
SPSCK
MOSI
MISO
SS
Chapter 13 Serial Peripheral Interface (S08SPIV3)
7
SLAVE
6
5
SPI SHIFTER
4
3
2
1
0
275
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