Z8F08200100KITG Zilog, Z8F08200100KITG Datasheet - Page 64
Z8F08200100KITG
Manufacturer Part Number
Z8F08200100KITG
Description
DEV KIT FOR Z8 ENCORE 8K/4K
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Datasheets
1.Z8F08200100KITG.pdf
(18 pages)
2.Z8F08200100KIT.pdf
(264 pages)
3.Z8F08200100KITG.pdf
(9 pages)
Specifications of Z8F08200100KITG
Contents
Evaluation Board, Cable, Power Supply, Software and Documentation
Silicon Manufacturer
Zilog
Core Architecture
Z8 Encore
Silicon Core Number
Z8F0822SJ020
Silicon Family Name
XP F0822
Rohs Compliant
Yes
For Use With/related Products
Z8 Encore!™
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4630
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Table 15. Port A–C Control Registers (PxCTL)
Table 16. Port A–C Data Direction Sub-Registers
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
Port A–C Control Registers
7
7
DD7
If 01H in Port A–C Address Register, accessible through the Port A–C Control Register
The Port A–C Control Registers set the GPIO port operation. The value in the correspond-
ing Port A–C Address Register determines the control sub-registers accessible using the
Port A–C Control Register
PCTL[7:0]—Port Control
The Port Control Register provides access to all sub-registers that configure the GPIO Port
operation.
Port A–C Data Direction Sub-Registers
The Port A–C Data Direction sub-register is accessed through the Port A–C Control
register by writing 01H to the Port A–C Address Register
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function
operation overrides the Data Direction register setting.
0 = Output. Data in the Port A–C Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–C Input
Port A–C Alternate Function Sub-Registers
The Port A–C Alternate Function sub-register
Port A–C Control Register by writing
Port A–C Alternate Function sub-registers select the alternate functions for the selected
Data Register. The output driver is tri-stated.
6
6
DD6
5
5
DD5
(Table
4
4
FD1H, FD5H, FD9H
DD4
15).
02H
PCTL
R/W
R/W
00H
1
3
3
to the Port A–C Address Register. The
DD3
(Table
17) is accessed through the
2
2
Z8 Encore! XP
DD2
(Table
General-Purpose Input/Output
Product Specification
16).
1
1
DD1
®
F0822 Series
0
0
DD0
51
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