DK-START-4CGX15N Altera, DK-START-4CGX15N Datasheet - Page 31

• Manufacturer Part Number: DK-START-4CGX15N
• Description: KIT STARTER CYCLONE IV GX
• Manufacturer: Altera
• Series: Cyclone® IVr
• Type: FPGAr

Specifications of DK-START-4CGX15N

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP4C
• Silicon Family Name: Cyclone IV GX
• Kit Contents: Board, Cables, PSU, CD
• Rohs Compliant: Yes
• For Use With/related Products: Cyclone IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2569

Chapter 6: Board Test System
Using the Board Test System
© March 2010 Altera Corporation
Data Pattern
The Data pattern control specifies the type of data contained in the transactions. The
following data types are available for analysis:
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Data Rate
The Data rate control specifies the speed of the transactions. The following data rates
are available for analysis:
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Control Register Settings
The Control register settings controls specify loopback test parameters. The
following settings are available for analysis:
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Status
These controls display current transaction performance analysis information collected
since you last clicked Start:
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PRBS 7—Selects pseudo-random 7-bit sequences.
PRBS 15—Selects pseudo-random 15-bit sequences.
PRBS 23—Selects pseudo-random 23-bit sequences.
PRBS 31—Selects pseudo-random 31-bit sequences.
PCIe compliance—Selects the repeating 40-bit PCIe compliance pattern:
/K28.5/D21.5/K28.5/D10.2/with the first /K28.5/ code group encoded with
negative current disparity (0011111010) to conform to the PCIe protocol. The
pattern is intended to be a signal loopback to demonstrate signal quality rather
than a complete PCIe compliance test.
1.25 Gbps—Selects a 1.25 Gbps transaction data rate.
2.5 Gbps—Selects a 2.5 Gbps transaction data rate.
Serial loopback—Routes signals back to the sender.
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VOD—Specifies the voltage output differential of the transmitter buffer.
Pre-emphasis—Specifies the amount of pre-emphasis on the transmitter buffer.
RX equalizer—Enables the static equalizer.
DC gain—Specifies the boost to incoming signals.
PLL lock—Shows the PLL locked or unlocked state.
Pattern sync—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
TX and RX performance bars—Show the percentage of maximum data rate that
the requested transactions are able to achieve.
Gbps—Shows the number of gigabits of data analyzed per second for transmit
and receive.
When off, use coaxial cables to loop the transceiver transmit signals (J10
and J11) back to the receiver signals (J8 and J9) for the test to work properly.
Cyclone IV GX Transceiver Starter Kit User Guide
6–13