MAX9218EVKIT+ Maxim Integrated Products, MAX9218EVKIT+ Datasheet - Page 6

• Manufacturer Part Number: MAX9218EVKIT+
• Description: KIT PCB EVALUATION FOR MAX9218
• Manufacturer: Maxim Integrated Products

Specifications of MAX9218EVKIT+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MAX9217/MAX9218 Evaluation Kit
pattern, connect a logic analyzer or data-acquisition sys-
tem to H1 and H2. See Table 4 for the output bit locations
on the H1 and H2 headers.
The MAX9218 DE_OUT pin is accessible through header
H2-21. A high output indicates that RGB_OUT[17:0] are
active and a low output indicates that CNTL_OUT[8:0]
are active.
The MAX9218 OUTEN pin is accessible through jumper
JU5. Drive the pin high by placing a shunt in the 1-4
Table_4._Video_and_Control_Data_Outputs
6_ _ _______________________________________________________________________________________
CNTL_OUT0
CNTL_OUT1
CNTL_OUT2
CNTL_OUT3
CNTL_OUT4
CNTL_OUT5
CNTL_OUT6
CNTL_OUT7
CNTL_OUT8
RGB_OUT0
RGB_OUT1
RGB_OUT2
RGB_OUT3
RGB_OUT4
RGB_OUT5
RGB_OUT6
RGB_OUT7
RGB_OUT8
RGB_OUT9
RGB_OUT10
RGB_OUT11
RGB_OUT12
RGB_OUT13
RGB_OUT14
RGB_OUT15
RGB_OUT16
RGB_OUT17
SIGNALS
OUTPUT_
DESIGNATION
Data-Enable Output (DE_OUT)
H2-11
H2-13
H2-15
H2-17
H2-19
H2-27
H2-29
H2-31
H1-11
H1-13
H1-15
H1-17
H1-19
H1-21
H1-23
H1-25
H1-27
H1-29
H1-31
H2-3
H2-5
H2-7
H2-9
H1-3
H1-5
H1-7
H1-9
Output Enable (OUTEN)
Output control bit 0
Output control bit 1
Output control bit 2
Output control bit 3
Output control bit 4
Output control bit 5
Output control bit 6
Output control bit 7
Output control bit 8
Output video bit 10
Output video bit 11
Output video bit 12
Output video bit 13
Output video bit 14
Output video bit 15
Output video bit 16
Output video bit 17
Output video bit 0
Output video bit 1
Output video bit 2
Output video bit 3
Output video bit 4
Output video bit 5
Output video bit 6
Output video bit 7
Output video bit 8
Output video bit 9
DESCRIPTION
position of JU5 to activate single-ended outputs. Drive
the pin low by placing a shunt in the 1-2 position of JU5
to place the single-ended outputs in high impedance.
The MAX9218 has a selectable rising or falling output
latch edge through logic setting on the R/F pin. Drive
the R/F pin low by placing a shunt in the 1-2 position of
jumper JU1 (see Table 1). Drive the R/F pin high by plac-
ing a shunt in the 1-4 position of JU1.
The parallel clock frequency range for the MAX9217 can
be configured through jumpers JU14 and JU15. Place a
shunt on JU14 and JU15 to drive RNG1 and RNG0 high,
or leave JU14 and JU15 unconnected to drive RNG1 and
RNG0 low. Refer to the MAX9217 IC data sheet for actual
frequency settings.
The operating frequency range for the MAX9218 can
be configured through jumpers JU2 and JU3. Place a
shunt in the 1-4 position of JU2 and JU3 to drive RNG1
and RNG0 high, or place a shunt in the 1-2 position of
JU2 and JU3 to drive RNG1 and RNG0 low. Refer to the
MAX9218 IC data sheet for actual frequency settings.
The power-down mode in the MAX9217 and MAX9218
puts the outputs in high impedance, stops the PLL, and
reduces supply current to 50FA or less.
The MAX9217 PWRDWN pin is accessible through
header H6-15. Drive the pin high for normal operation
of the MAX9217 or drive the pin low to power down the
MAX9217.
The MAX9218 PWRDWN pin is accessible through
jumper JU4 (see Table 1). Drive the pin high by placing
a shunt in the 1-4 position of JU4 for normal operation.
Drive the pin low by placing a shunt in the 1-2 position of
JU4 to power down the MAX9218.
The MAX9217/MAX9218 EV kit offers the user an internal
test mode to quickly check full functionality and verify
the quality of the SerDes link. This mode is called the
pseudo-random bit sequence, or PRBS mode.
The MAX9217 features an on-chip PRBS generator that
can be utilized to generate a pseudo-random bit stream
to evaluate the quality and performance by comparing
the output of the serializer (prior to the link/cable) with the
input of the deserializer (after the link/cable).
Frequency Range Setting (RNG1 and RNG0)
Pseudo-Random Bit Sequence (PRBS) Mode
Rising and Falling Input Latch Edge (R/F)
Power-Down (PWRDWN)