KSZ8001L-EVAL Micrel Inc, KSZ8001L-EVAL Datasheet - Page 13

• Manufacturer Part Number: KSZ8001L-EVAL
• Description: BOARD EVALUATION FOR KSZ8001L
• Manufacturer: Micrel Inc

Specifications of KSZ8001L-EVAL

• Main Purpose: Interface, Ethernet PHY
• Embedded: No
• Utilized Ic / Part: KSZ8001L
• Primary Attributes: Single Chip PHY, 100BASE-TX/100BASE-FX/10BASE-T
• Secondary Attributes: MII, RMII, SMII, HP Auto MDI, MDI-X Auto Polarity Correction, LinkMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1620

March 2006
Micrel
SQE and Jabber Function (10BASE-T only)
In 10BASE-T operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required as a test of the
10BASE-T transmit/receive path and is called SQE test. The 10BASE-T transmitter will be disabled and COL will go high if TXEN is
High for more than 20 ms (Jabbering). If TXEN then goes low for more than 250 ms, the 10BASE-T transmitter will be re-enabled
and COL will go Low.
Auto-Negotiation
The KSZ8001 performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It will automatically
choose its mode of operation by advertising its abilities and comparing them with those received from its link partner whenever auto-
negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in either full- or half-duplex mode. Auto-
negotiation is disabled in FX mode.
During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under the
conditions of power-on, link-loss or re-start. At the same time, the KSZ8001 will monitor incoming data to determine its mode of
operation. Parallel detection circuit will be enabled as soon as either 10BASE-T NLP (Normal Link Pulse) or 100BASE-TX idle is
detected. The operation mode is configured based on the following priority:
When the KSZ8001 receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge bit), it will
store these code words in Register 5 and wait for the next 3 identical code words. Once the KSZ8001 detects the second code
words, it then configures itself according to the above-mentioned priority. In addition, the KSZ8001 also checks for 100BASE-TX idle
or 10BASE-T NLP symbols. If either is detected, the KSZ8001 automatically configures to match the detected operating speed.
MII Management Interface
The KSZ8001 supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO)
Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8001. The MDIO interface consists of
the following:
The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status change on
the KSZ8001 based upon 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register bits at 1bh[7:0] are the
interrupt condition bits. This interrupt is cleared by reading Register 1bh.
MII Data Interface
The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Controller (MAC)
to the KSZ8001, and for receiving data from the line. Normal data transmission is implemented in 4B Nibble Mode (4-bit wide
nibbles).
Transmit Clock (TXC): The transmit clock is normally generated by the KSZ8001 from an external 25MHz reference source at the
X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KSZ8001 normally
samples these signals on the rising edge of the TXC.
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Priority 1: 100BASE-TX, full-duplex
Priority 2: 100BASE-TX, half-duplex
Priority 3: 10BASE-T, full-duplex
Priority 4: 10BASE-T, half-duplex
A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT)
A specific protocol that runs across the above-mentioned physical connection and it also allows one controller to
communicate with multiple KSZ8001 devices. Each KSZ8001 is assigned an MII address between 0 and 31 by the PHYAD
inputs.
An internal addressable set of fourteen 16-bit MDIO registers. Register [0:6] are required and their functions are specified
by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.
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Revision 1.03
KSZ8001