MT16HTF25664AY-667E1 Micron Technology Inc, MT16HTF25664AY-667E1 Datasheet - Page 18

• Manufacturer Part Number: MT16HTF25664AY-667E1
• Description: MODULE DDR2 2GB 240-UDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16HTF25664AY-667E1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 667MT/s
• Package / Case: 240-UDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1347

Table 14: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
PDF: 09005aef80f09084
htf16c64_128_256x64ay.pdf - Rev. G 3/10 EN
Parameter
Operating one bank active-precharge current:
=
valid commands; Address bus inputs are switching; Data bus inputs
are switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
t
valid commands; Address bus inputs are switching; Data pattern is
same as I
Precharge power-down current: All device banks idle;
(I
ta bus inputs are floating
Precharge quiet standby current: All device banks idle;
(I
are stable; Data bus inputs are floating
Precharge standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are
switching; Data bus inputs are switching
Active power-down current: All device banks open;
t
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
=
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous
burst read, I
t
tween valid commands; Address bus inputs are switching; Data bus
inputs are switching
Burst refresh current:
t
Other control and address bus inputs are switching; Data bus inputs
are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control
and address bus inputs are floating; Data bus inputs are floating
RAS MIN (I
CK =
RAS =
RFC (I
DD
DD
t
t
RC (I
RAS MAX (I
); CKE is LOW; Other control and address bus inputs are stable; Da-
); CKE is HIGH, S# is HIGH; Other control and address bus inputs
t
DD
CK (I
DD
DD
t
RAS MAX (I
) interval; CKE is HIGH, S# is HIGH between valid commands;
DD4W
),
),
DD
DD
t
t
RP =
RAS =
OUT
),
); CKE is LOW; Other control and address
DD
t
= 0mA; BL = 4, CL = CL (I
RCD =
),
DD
t
RP (I
t
t
), AL = 0;
RP =
RAS MIN (I
DD
DD
),
DD
t
Specifications and Conditions (Die Revision E) – 2GB
RCD (I
t
t
RP =
t
); CKE is HIGH, S# is HIGH between valid com-
RP (I
CK =
t
CK =
DD
t
DD
DD
DD
RP (I
t
CK (I
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
), AL = 0;
); CKE is HIGH, S# is HIGH between
t
DD
CK (I
DD
); CKE is HIGH, S# is HIGH be-
); REFRESH command at every
DD
DD
t
),
CK =
), AL = 0;
512MB, 1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 UDIMM
t
RC =
t
CK (I
t
t
RC (I
CK =
t
CK =
t
t
DD
CK =
CK =
DD
),
t
CK (I
t
t
),
Fast PDN exit
MR[12] = 0
Slow PDN ex-
it MR[12] = 1
RAS =
CK (I
t
t
OUT
CK =
t
CK (I
t
t
CK (I
RAS =
CK =
18
DD
= 0mA;
DD
DD
),
t
DD
t
CK
RAS
),
t
t
CK
),
);
RAS
t
RC
Micron Technology, Inc. reserves the right to change products or specifications without notice.
I
I
I
I
I
Sym-
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
bol
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
-1GA
1096
1120
1736
1736
4240
976
112
960
960
800
160
112
-80E/
-800
1336
1336
3760
776
936
112
800
800
640
160
960
112
© 2003 Micron Technology, Inc. All rights reserved.
-667
1136
1136
3440
736
856
112
640
640
480
160
880
112
I
DD
Specifications
1056
1056
3360
-53E
616
816
112
640
640
180
160
720
112
-40E Units
3280
616
776
112
560
560
480
160
640
896
896
112
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA