MT5LSDT472AG-133G6 Micron Technology Inc, MT5LSDT472AG-133G6 Datasheet - Page 9

• Manufacturer Part Number: MT5LSDT472AG-133G6
• Description: MODULE SDRAM 32MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT5LSDT472AG-133G6

• Memory Type: SDRAM
• Memory Size: 32MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 7:
NOTE:
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
Page (y)
1. For full-page accesses: y = 256 (32MB); y = 512 (64MB/
2. For a burst length of two, A1–Ai select the block-of-
3. For a burst length of four, A2–Ai select the block-of-
4. For a burst length of eight, A3–Ai select the block-of-
5. For a full-page burst, the full row is selected and
6. Whenever a boundary of the block is reached within a
7. For a burst length of one, A0–Ai select the unique col-
8. i = 7 for 32MB module
LENGTH
BURST
Full
128MB).
two burst; A0 selects the starting column within the
block.
four burst; A–A1 select the starting column within the
block.
eight burst; A0–A2 select the starting column within
the block.
A0–Ai select the starting column.
given sequence above, the following access wraps
within the block.
umn to be accessed, and mode register bit M3 is
ignored.
i = 8 for 64MB and 128MB modules
2
4
8
A2 A1 A0
STARTING
ADDRESS
0
0
0
0
1
1
1
1
COLUMN
n = A0-Ai
(location
0-y)
A1 A0
Burst Definition Table
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn + 4. . . Cn - 1,
ORDER OF ACCESSES WTHIN A
SEQUENTIAL
Cn + 2, Cn + 3,
Cn, Cn + 1,
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn . . .
0-1
1-0
BURST
3-4-5-6-7-0-1-2-
INTERLEAVED
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
9
CAS Latency
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
and the latency is m clocks, the data will be available
by clock edge n + m. The DQ will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQ will start driving after T1 and the data
will be valid by T2, as shown in Figure 5, CAS Latency
Diagram, on page 9. The CAS Latency Table indicates
the operating frequencies at which each CAS latency
setting can be used.
operation or incompatibility with future versions may
result.
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
32MB, 64MB, 128MB (x72, SR)
CLK
CLK
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
READ
READ
T0
T0
168-PIN SDRAM UDIMM
CAS Latency = 2
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
©2004 Micron Technology, Inc. All rights reserved.
T2
T2
NOP
NOP
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4