MT36VDDF12872G-40BG3 Micron Technology Inc, MT36VDDF12872G-40BG3 Datasheet - Page 23

• Manufacturer Part Number: MT36VDDF12872G-40BG3
• Description: MODULE SDRAM DDR 1GB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36VDDF12872G-40BG3

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef80772fd2, source: 09005aef8075ebf6
DDF36C128_256x72G.fm - Rev. D 9/04 EN
30.
31. READs and WRITEs with auto precharge are not
32. Any positive glitch to nominal must be less than
33. Normal Output Drive Curves:
160
140
120
100
Figure 11: Pull-Down Characteristics
80
60
40
20
0
0.0
t
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
allowed to be issued until
fied prior to the internal precharge command
being issued.
1/3 of the clock and not more than +400mV or
2.9V maximum, whichever is less. Any negative
glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.2V minimum,
whichever is more positive.
HP min is the lesser of
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current
d. The variation in driver pull-up current within
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 11,
Pull-Down Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 11, Pull-Down Characteristics.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 12,
Pull-Up Characteristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
12, Pull-Up Characteristics.
0.5
1.0
V
V
OUT
OUT
(V)
(V)
t
t
CL minimum and
RAS (MIN) can be satis-
1.5
2.0
Minimum
t
CH
2.5
23
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialization, V
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
Figure 12: Pull-Up Characteristics
0.0
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
equal to or less than V
may be 1.35V maximum during power up, even if
V
series resistance is used between the V
and the input pin.
e. The full variation in the ratio of the maximum
f. The full variation in the ratio of the nominal
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and tRPRE begin point are not
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
IL
DD
RPST), or begins driving (
DD
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
(MIN) = -1.5V for a pulse width
/V
overshoot: V
and V
t
DQSCK (MIN) +
DDQ
DD
1GB, 2GB (x72, ECC, DR)
0.5
DDQ
are 0V, provided a minimum of 42 of
level and the referenced test load. In
3ns and the pulse width can not be
184-PIN DDR RDIMM
must track each other.
IH
1.0
V
(MAX) = V
DD
t
DD
Q - V
RPRE (MAX) condition.
DDQ
©2004 Micron Technology, Inc. All rights reserved.
OUT
+ 0.3V. Alternatively, V
t
t
, V
LZ (MIN) will prevail
(V)
RPRE).
1.5
TT
t
, and V
DD
DQSCK (MAX) +
Q + 1.5V for a
IL
undershoot:
3ns and the
REF
2.0
TT
must be
supply
TT
2.5