MT36VDDF12872G-26AG3 Micron Technology Inc, MT36VDDF12872G-26AG3 Datasheet - Page 11

• Manufacturer Part Number: MT36VDDF12872G-26AG3
• Description: MODULE SDRAM DDR 1GB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36VDDF12872G-26AG3

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 266MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
A3 specifies the type of burst (sequential or inter-
leaved), A4–A6 specify the CAS latency, and A7–A12
specify the operating mode.
Burst Length
burst oriented, with the burst length being program-
mable, as shown in Figure 7, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see Note 5, of Table 8, Burst Definition
Table, on page 12). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both READ and WRITE bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
pdf: 09005aef80772fd2, source: 09005aef8075ebf6
DDF36C128_256x72G.fm - Rev. D 9/04 EN
Mode register bits A0–A2 specify the burst length,
Read and write accesses to DDR SDRAM devices are
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
11
mined by the burst length, the burst type and the start-
ing column address, as shown in Figure 8, Burst
Definition Table, on page 12.
* M14 and M13 (BA1 and BA0)
must be 0, 0 to select the
base mode register (vs. the
extended mode register).
The ordering of accesses within a burst is deter-
Figure 7: Mode Register Definition
0*
14
BA1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
13
BA0
12
A12 A11
Operating Mode
11
10
1GB, 2GB (x72, ECC, DR)
A10
M12 M11
0
0
-
9
A9
0
0
-
8
A8
184-PIN DDR RDIMM
M10
0
0
-
Diagram
7
A7 A6 A5 A4 A3
M9
M6
0
0
-
CAS Latency BT
0
0
0
0
1
1
1
1
6
M8 M7
0
1
M5
-
0
0
1
1
0
0
1
1
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
©2004 Micron Technology, Inc. All rights reserved.
M3
M6-M0
0
1
Valid
Valid
3
-
Burst Length
M2
2
0
0
0
0
1
1
1
1
CAS Latency
A2 A1 A0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
2.5
2
M0
0
1
0
1
0
1
0
1
0
Burst Type
Interleaved
Sequential
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
M3 = 0
Address Bus
2
4
8
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 1
2
4
8