MT5VDDT3272AY-335F1 Micron Technology Inc, MT5VDDT3272AY-335F1 Datasheet - Page 4

• Manufacturer Part Number: MT5VDDT3272AY-335F1
• Description: MODULE DDR 256MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT5VDDT3272AY-335F1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 975mA
• Number Of Elements: 5
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7:
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
RAS#, CAS#, WE#
(DQS9–DQS17)
DQS0–DQS7
DQ0–DQ63
CK0, CK0#,
CK1, CK1#,
DM0–DM8
CK2, CK2#
V
BA0, BA1
SA0–SA2
CB0–CB7
Symbol
A0–A12
DD
V
CKE1
SDA
DDSPD
V
S0#
SCL
V
NC
/V
Pin Descriptions
REF
SS
DD
Q
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
–
Description
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command. A0–A11 (64MB) and A0–A12 (128MB, 256MB).
Bank address: BA0 and BA1 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK
and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)
deactivates the internal clock, input buffers, and output drivers.
Data input mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, during a write
access. DM is sampled on both edges of DQS. Although DM pins are input-only,
the DM loading is designed to match that of DQ and DQS pins.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Chip selects: S# (registered LOW) enables and (registered HIGH) disables the
command decoder.
Presence-detect address inputs: These pins are used to configure the
presence-detect device.
Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
Check bits.
Data input/output: Data bus.
Data strobe: Output with read data, input with write data. DQS is edge-
aligned with read data, center-aligned with write data. Used to capture data.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
Serial EEPROM positive power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (V
Ground.
No connect: These pins are not connected on the module.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
/2).
Pin Assignments and Descriptions
©2002 Micron Technology, Inc. All rights reserved.