MT8VDDT3264HG-335G3 Micron Technology Inc, MT8VDDT3264HG-335G3 Datasheet - Page 20

• Manufacturer Part Number: MT8VDDT3264HG-335G3
• Description: MODULE DDR SDRAM 256MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT3264HG-335G3

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 167MHz
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1123

pdf: 09005aef8092973f, source: 09005aef80921669
DD8C16_32_64x64HG.fm - Rev. B 9/04 EN
30.
31. READs and WRITEs with auto precharge are not
32. Any positive glitch in the nominal voltage must be
33. Normal Output Drive Curves:
160
140
120
100
80
60
40
20
Figure 8: Pull-Down Characteristics
0
0.0
t
minimum actually applied to the device CK and
CK/ inputs, collectively during device bank active.
allowed to be issued until
fied prior to the internal precharge command
being issued.
less than 1/3 of the clock and not more than
+400mV or 2.9V maximum, whichever is less. Any
negative glitch must be less than 1/3 of the clock
cycle and not exceed either -300mV or 2.2V mini-
mum, whichever is more positive.
HP min is the lesser of
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current
d. The variation in driver pull-up current within
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Down Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 8, Pull-Down Characteristics.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Up Characteristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
9, Pull-Up Characteristics.
0.5
1.0
V
V
OUT
OUT
(V)
(V)
t
t
CL minimum and
RAS(MIN) can be satis-
1.5
2.0
Minimum
t
CH
2.5
20
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialization, V
128MB, 256MB, 512MB (x64, SR)
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
42
supply and the input pin.
Figure 9: Pull-Up Characteristics
e. The full variation in the ratio of the maximum
f. The full variation in the ratio of the nominal
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
IL
DD
RPST), or begins driving (
TT
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
(MIN) = -1.5V for a pulse width
overshoot: V
and V
may be 1.35V maximum during power up,
t
of series resistance is used between the V
DQSCK (MIN) +
DD
DD
0.5
DD
level and the referenced test load. In
/V
200-PIN DDR SODIMM
Q must track each other.
DD
3ns and the pulse width can not be
Q are 0V, provided a minimum of
IH
1.0
V
(MAX) = V
DD
t
Q - V
RPRE (MAX) condition.
t
RPRE begin point are not
DD
©2004 Micron Technology, Inc. All rights reserved.
OUT
DD
t
Q, V
t
LZ (MIN) will prevail
(V)
RPRE).
1.5
+ 0.3V. Alternatively,
TT
t
DD
DQSCK (MAX) +
, and V
Q + 1.5V for a
IL
undershoot:
3ns and the
2.0
REF
must
TT
2.5