MT16VDDT12864AY-335F2 Micron Technology Inc, MT16VDDT12864AY-335F2 Datasheet - Page 21

• Manufacturer Part Number: MT16VDDT12864AY-335F2
• Description: MODULE DDR 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDT12864AY-335F2

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.44A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
140.6µs (256MB) or 70.3µs (512MB, 1GB, 2GB);
burst refreshing or posting by the DRAM control-
ler greater than eight refresh cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Figure 8, Derating Data Valid Window
t
ranging between 50/50 and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
HP -
a. Sustain a constant slew rate from the current
t
QH =
AC level through to the target AC level, V
or V
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
QHS, shows derating curves for duty cycles
t
IH
HP -
50/50
(AC).
3.750
2.500
t
QHS). The data valid window derates
NA
49.5/50.5
3.700
-262/-26A/-265 @
-262/-26A/-265 @
-335 @
2.463
t
HP (
t
CK = 6ns
t
Figure 8: Derating Data Valid Window
CK/2),
49/51
3.650
2.425
t
t
t
CK = 10ns
CK = 7.5ns
RFC [MIN]) else
t
DQSQ, and
48.5/52.5
3.600
2.388
IL
(AC)
3.550
48/52
t
QH
t
2.350
HP -
Clock Duty Cycle
21
256MB, 512MB, 1GB, 2GB (x64, DR)
t
47.5/53.5
QHS
3.500
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
2.313
be 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncer-
tain.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
DH for each 100mv/ns reduction in slew rate. If
HP min is the lesser of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
184-PIN DDR SDRAM UDIMM
maintain at least the target DC level, V
or V
3.450
47/53
must not vary more than 4 percent if CKE is
2.275
IH
(DC).
46.5/54.5
3.400
2.238
3.350
46/54
2.200
t
CL minimum and
45.5/55.5
3.300
2.163
©2004 Micron Technology, Inc.
3.250
45/55
2.125
t
DS and
IL
(DC)
t
CH