TC58V64BDC Toshiba, TC58V64BDC Datasheet - Page 15

• Manufacturer Part Number: TC58V64BDC
• Description: IC 64MBIT NAND FLASH 3V 44-TSOP
• Manufacturer: Toshiba

Specifications of TC58V64BDC

• Memory Size: 8MB
• Memory Type: EEPROM - Smart Media
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN FUNCTIONS
pin-outs are configured as shown in Figure 1.
The device is a serial access memory which utilizes time-sharing input of address information. The device
Command Latch Enable: CLE
operation mode command into the internal command register.
The command is latched into the command register from the I/O
port on the rising edge of the WE signal while CLE is High.
Address Latch Enable: ALE
information or input data into the internal address/data register.
Address information is latched on the rising edge of WE if ALE
is High. Input data is latched if ALE is Low.
Chip Enable:
goes High during a Read operation. The CE signal is ignored
when device is in Busy state (
Standby mode even if the CE input goes High. The CE signal must stay Low during the Read mode Busy
state to ensure that memory array data is correctly transferred to the data register.
Write Enable:
Read Enable:
The internal column address counter is also incremented (Address = Address + 1) on this falling edge.
I/O Port: I/O1~I/O8
the device.
Write Protect:
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
Busy state (
(
Low Voltage Detect: LVD
RY
The CLE input signal is used to control loading of the
The ALE signal is used to control loading of either address
The device goes into a low-power Standby mode when CE
The WE signal is used to control the acquisition of data from the I/O port.
The RE signal controls serial data output. Data is available t
The I/O1 to I/O8 pins are used as a port for transferring address, command and input/output data to and from
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
The
The LVD signal is used to detect the power supply voltage level.
/
BY
RY
= H) after completion of the operation. The output buffer for this signal is an open drain.
/
BY
RY
RY
output signal is used to indicate the operating condition of the device. The
CE
/
RE
BY
WE
WP
/
BY
= L) during the Program, Erase and Read operations and will return to Ready state
RY
/
BY
= L), such as during a Program or Erase operation, and will not enter
REA
V
22
CC
V
after the falling edge of RE .
1
SS
CE RE
21
CLE ALE
2
20
3
RY
WE WP
19
/
4
BY
Figure 1. Pinout
GND LVD I/O8 I/O7 I/O6 I/O5 V
5
18
2001-10-24 15/33
I/O1 I/O2 I/O3 I/O4 V
6
17
TC58V64BDC
RY
7
16
/
BY
8
15
9
signal is in
14
10
SS
13
V
11
SS
12
CC