KS8995MA Micrel Inc, KS8995MA Datasheet - Page 38

• Manufacturer Part Number: KS8995MA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995MA

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1017 - BOARD EVAL EXPERIMENT KS8995M
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

KS8995MA
MII Management Interface (MIIM)
A standard MIIM interface is provided for all five PHY devices in the KS8995MA. An external device with MDC/MDIO capability
is able to read PHY status or to configure PHY settings. For details on the MIIM interface standard please reference the IEEE
802.3 specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in the
KS8995MA. It can only access the standard MII registers. See “MIIM Registers.” The SPI interface, on the other hand, can
be used to access the entire KS8995MA feature set.
M9999-051305
SPIS_N
SPIS_N
SPIS_N
SPIS_N
SPIC
SPID
SPIQ
SPIC
SPID
SPIQ
SPIC
SPID
SPIQ
SPIC
SPID
SPIQ
D7
X
X
D7
X
D6
X
0
D6
0
D5
0
X
D5
READ COMMAND
Byte 2
0
D4
0
X
D4
Byte 2
WRITE COMMAND
0
D3
0
X
D4
0
D2
X
D2
0
0
D1
X
D1
0
0
Figure 10. SPI Multiple Write
Figure 11. SPI Multiple Read
D0
1
X
D0
1
D7
1
X
D7
0
A7 A6 A5 A4 A3 A2 A1 A0
D6
X
D6
A7 A6 A5 A4 A3 A2 A1 A0
D5
X
D5
READ ADDRESS
Byte 3 ...
38
Byte 3 ...
D4
X
D4
WRITE ADDRESS
D3
X
D3
D2
X
D2
D1
X
D1
D0
X
D0
D7
X
D7
X
D7
D7
D6
X
D6
X
D6
D6
D5
X
D5
X
Byte 1
D5
D5
Byte N
D4
X
D4
X
D4
D4
Byte N
Byte 1
D3
X
D3
X
D3
D3
D2
X
D2
X
D2
D2
D1
X
D1
X
D1
D1
D0
X
D0
X
D0
D0
Micrel, Inc.
May 2005