KS8995MA Micrel Inc, KS8995MA Datasheet - Page 28

• Manufacturer Part Number: KS8995MA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995MA

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1017 - BOARD EVAL EXPERIMENT KS8995M
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

KS8995MA
The MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode. These
interfaces are nibble-wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on the
transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators
that convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicates
a collision has occurred during transmission.
Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is not
provided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming from the
physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this
configuration. For PHY mode operation, if the device interfacing with the KS8995MA has an MRXER pin, it should be tied low.
For MAC mode operation, if the device interfacing with the KS8995MA has an MTXER pin, it should be tied low.
SNI Interface Operation
The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This interface
can be directly connected to these types of devices. The signals are divided into two groups, one for transmission and the other
for reception. The signals involved are described in Table 3.
This interface is a bit-wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the
transmit side indicates when data is valid. Likewise, the receive side also has an indicator that shows if the data it is receiving
is valid.
For half-duplex operation, there is a signal that indicates if a collision has occurred during transmission.
Advanced Functionality
Spanning Tree Support
Port 5 is the designated port for spanning tree support.
The other ports (port 1 – port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive enable,”
and “learning disable” register settings in Registers 18, 34, 50, and 66 for ports 1, 2, 3, and 4, respectively. The following
description shows the port setting and software actions taken for each of the five spanning tree states.
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to the
processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard those
packets. Note: processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1"
Software action: the processor should not send any packets to the port(s) in this state. The processor should program the
“Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should also be set so that
the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor
may send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is disabled on
the port in this state.
M9999-051305
SNI Signal
TXEN
TXD
TXC
COL
CRS
RXD
RXC
Description
Transmit enable
Serial transmit data
Transmit clock
Collision detection
Carrier sense
Serial receive data
Receive clock
Table 3. SNI Signals
28
SMTXEN
SMTXD[0]
SMRXD[0]
KS8995MA Signal
SMTXC
SCOL
SMRXDV
SMRXC
Micrel, Inc.
May 2005