KS8995MA Micrel Inc, KS8995MA Datasheet - Page 18

• Manufacturer Part Number: KS8995MA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995MA

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1017 - BOARD EVAL EXPERIMENT KS8995M
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

KS8995MA
M9999-051305
Note:
1. P = Power supply.
2. PU = Strap pin pull-up.
Pin Number
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/ internal pull-up.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
Otri = Output tristated.
NC = No connect.
PD = Strap pin pull-down.
Fulld = Full duplex.
86
85
78
83
82
81
80
79
75
73
72
71
70
69
74
Pin Name
SMRXDV
SMRXD0
SMRXD1
SMRXD2
SMRXD3
SMTXEN
SMTXER
SCONF1
SMTXD0
SMTXD1
SMTXD2
SMTXD3
SMRXC
SMTXC
SCRS
Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
I/O
(1)
Port
Pin Function
Dual MII configuration pin.
Pin (91, 86, 87):
000
001
010
011
100
101
110
111
Switch MII carrier sense.
Switch MII receive clock. Input in MAC mode, output in PHY mode MII.
Switch MII receive bit 0; strap option: LED mode
PD (default) = mode 0; PU = mode 1. See “Register 11.”
LEDX_2
LEDX_1
LEDX_0
Switch MII receive bit 1. Strap option: PD (default) = switch MII in
100Mbps mode; PU = switch MII in 10Mbps mode.
Switch MII receive bit 2. Strap option: PD (default) = switch MII in
full-duplex mode; PU = switch MII in half-duplex mode.
Switch MII receive bit 3. Strap option: PD (default) = disable switch
MII full-duplex flow control; PU = enable switch MII full-duplex flow control.
Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.
Switch MII transmit bit 0.
Switch MII transmit bit 1.
Switch MII transmit bit 2.
Switch MII transmit bit 3.
Switch MII transmit enable.
Switch MII transmit error.
Switch MII receive data valid.
18
(2)
Switch MII
Disable, Otri
PHY Mode MII
MAC Mode MII
PHY Mode SNI
Disable
PHY Mode MII
MAC Mode MII
PHY Mode SNI
PHY [5] MII
Disable, Otri
Disable, Otri
Disable, Otri
Disable, Otri
Disable
PHY Mode MII
PHY Mode MII
PHY Mode MII
Mode 0
Lnk/Act
Fulld/Col
Speed
Mode 1
100Lnk/Act
10Lnk/Act
Full duplex
Micrel, Inc.
May 2005