AD5520JST Analog Devices Inc, AD5520JST Datasheet - Page 6

• Manufacturer Part Number: AD5520JST
• Description: IC SNGL PARAMETRIC MEASURE64LQFP
• Manufacturer: Analog Devices Inc
• Type: Per-pin Parametric Measurement Unit (PPMU)r

Specifications of AD5520JST

• Rohs Status: RoHS non-compliant
• Applications: Automatic Test Equipment
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• For Use With: EVAL-AD5520EBZ - BOARD EVAL FOR AD5520
• Lead Free Status / RoHS Status: Not Compliant

AD5520
TIMING CHARACTERISTICS
AV
noted.
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
1
2
3
4
5
6
7
8
9
10
11
12
13
See Figure 2.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
CC
= +15 V ± 5%, AV
1, 2
AMx, ACx, FSEL,
MSEL, CPSEL
CLHDETECT,
CPOL, CPOH
CLLDETECT
QM4, QM5,
CPCK
STB
CS
5 V ± 10%
0
30
40
0
550
320
450
150
100
240
150
100
320
EE
= −15 V ± 5%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All specifications 0°C to 70°C, unless otherwise
DV
t
t
DD
1
4
OR MEASIOUT
0
200
70
560
320
500
800
440
240
320
CPOH, CPOL
3.3 V
40
500
440
MEASVOUT
t
CPCK
2
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
ns min
ns min
ns min
t
t
6
DD
3
) and timed from a voltage level of (V
Figure 3. Comparator Timing
t
10
Figure 2. Timing Diagram
Rev. B | Page 6 of 24
t
12
Conditions/Comments
CS falling edge to STB falling edge setup time
STB pulse width
STB rising edge to CS rising edge setup time
Data setup time
CS falling edge to CPCK rising edge setup time
CPCK pulse width
CPCK to STB falling edge setup time
STB rising edge to QMx, CLxDETECT valid
STB rising edge to CPOH, CPOL valid
Comparator setup time, MODE2, MODE3 settling
Comparator hold time
Comparator output delay time
Comparator strobe pulse width
t
11
t
5
t
13
t
6
IL
+ V
t
IH
7
)/2.
t
9