IDT72P51369L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51369L6BBI8 Datasheet - Page 10

• Manufacturer Part Number: IDT72P51369L6BBI8
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51369L6BBI8

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.7ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Supply Current: 150mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51369L6BBI8

PIN DESCRIPTIONS
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
BM [3:0]
(J1, L14,15,16)
D[35:0]
Din
(See Pin No.
table for details)
DF
(L3)
DFM
(L2)
EF/OR
(P9)
ESTR
(R15)
ESYNC
(R16)
EXI
(T16)
EXO
(T15)
Symbol &
(Pin No.)
(1)
(1)
Bus Matching
Data Input Bus
Default Flag
Default Mode
Empty Flag/
Output Ready
PAEn Flag Bus HSTL-LVTTL If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK
Strobe
PAEn Bus Sync HSTL-LVTTL ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus
PAEn Bus
Expansion In
PAEn Bus
Expansion Out
Name
HSTL-LVTTL These pins define the bus width of the input write port and the output read port of the device. The bus
HSTL-LVTTL These are the 36 data input pins. Data is written into the device via these input pins on the rising edge
HSTL-LVTTL If the user requires default programming of the multi-queue device, this pin must be setup before Master
HSTL-LVTTL The multi-queue device requires programming after master reset. The user can do this serially via the
HSTL-LVTTL This signal is bi-modal. When IDT Standard mode is selected the pin provides Empty Flag (EF) status.
HSTL-LVTTL The EXI input is used when multi-queue devices are connected in expansion configuration and Polled
HSTL-LVTTL EXO is an output that is used when multi-queue devices are connected in expansion configuration and
I/O TYPE
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
and the RDADD bus to select a status word of queues to be placed on to the PAEn bus outputs. A status
widths are set during a Master Rest cycle. The BM[3:0] signals must meet the setup and hold time
requirements of Master Reset and must not toggle/change state after a Master Reset cycle.
of WCLK provided that WEN is LOW. Note, that in Packet mode D32-D35 may be used as packet
markers, please see packet ready functional discussion for more detail. Due to bus matching not all inputs
may be used, any unused inputs should be tied LOW.
D[35] Transmit End of Packet (TEOP)
D[34] Transmit Start of Packet (TSOP)
D[33:32] User definable bits
D[31:0] Data input bits
Reset and must not toggle during any device operation. The state of this input at master reset determines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
serial port, or via parallel programming or by the default programming option The default programming
option provides a pre-defined configuration. If DFM is LOW at master reset then serial mode will be
selected, if HIGH then default mode is selected.
When FWFT mode is selected the pin provides output ready (OR) status. This output flag provides Output
Ready status for the data word present on the multi-queue flow-control device data output bus, Qout in
FWFT mode. This flag is a 2-stage delayed to match the data output path delay. There is a 3 RCLK cycle
delay in IDT Standard mode and a 4 cycle delay for FWFT mode from the time a given queue is selected
for reads, to the time the OR flag represents the data in that queue. When a selected queue on the read port
is read to empty, the OR flag will go HIGH, indicating that data on the output bus is not valid. The OR flag also
has High-Impedance capability, required when multiple devices are used and the OR flags are tied together.
word addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH.
If Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus
selection cannot be made, (ESTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
during Polled operation of the PAEn bus. During Polled operation each status word of queue status flags
is loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads
status word 1 on to PAEn, the second RCLK rising edge loads status word 2 and so on. The fifth RCLK
rising edge will again load status word 1. During the RCLK cycle that status word 1 of a selected device
is placed on to the PAEn bus, the ESYNC output will be HIGH. For all other status words of that device,
the ESYNC output will be LOW.
PAEn bus operation has been selected . EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The
EXI receives a token from the previous device in a chain. In single device mode the EXI input must be tied
LOW if the PAEn bus is operated in direct mode. If the PAEn bus is operated in polled mode the EXI
input must be connected to the EXO output of the same device. In expansion configuration the EXI of
the first device should be tied LOW, when direct mode is selected.
Polled PAEn bus operation has been selected . EXO of device ‘N’ connects directly to EXI of device ‘N+1’.
This pin pulses when device N has placed its final (4th) status word on to the PAEn bus with respect to
RCLK. This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK
rising edge the first status word of device N+1 will be loaded on to the PAEn bus. This continues through
the chain and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of
each device in the chain provides synchronization to the user of this looping event.
10
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AUGUST 4, 2005