IDT72V51233L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51233L7-5BB8 Datasheet - Page 8

• Manufacturer Part Number: IDT72V51233L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51233L7-5BB8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51233L7-5BB8

PIN DESCRIPTIONS (CONTINUED)
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PAE
(P10)
PAEn
(PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
PAF
(R8)
PAFn
(PAE3-P5
PAE2-R5
PAE1-T5
PAE0-T4)
PRS
(T8)
Q[17:0]
Qout (See Pin
table for details)
RADEN
(R14)
RCLK
(T10)
RDADD
[5:0]
(See next page
for details)
Symbol &
Pin No.
Programmable
Almost-Empty Flag OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
Programmable
Almost-Empty
Flag Bus
Programmable
Almost-Full Flag
Programmable
Almost-Full
Flag Bus
Partial Reset
Data Output Bus
Read Address
Enable
Read Clock
Read Address Bus
Name
I/O TYPE
OUTPUT selected device. During queue read/write operations these outputs provide programmable empty flag
OUTPUT write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue
OUTPUT selected device. During queue read/write operations these outputs provide programmable full flag status,
OUTPUT of RCLK provided that REN is LOW, OE is LOW and the queue is selected. Due to bus matching not
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
INPUT
LVTTL
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is
synchronized to RCLK.
On the 4Q device the PAEn bus is 4 bits wide. This output bus provides PAE status of all 4 queues, within a
status in either director polled mode. The mode of flag operation is determined during master reset via
the state of the FM input. This flag bus is capable of High-Impedance state, this is important during expansion
of multi-queue devices. During direct operation the PAEn bus is updated to show the PAE status of queues
within a selected device. Selection is made using RCLK, ESTR and Flag Bus RDADD. During Polled
operation the PAEn bus is loaded with the PAE status of multi-queue flow-control devices sequentially
based on the rising edge of RCLK.
This pin provides the Almost-Full flag status for the queue that has been selected on the input port for
is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is synchronized
to WCLK.
On the 4Q device the PAFn bus is 4 bits wide. This output bus provides PAF status of all 4 queues, within a
in either direct or polled mode. The mode of flag operation is determined during master reset via the state
of the FM input. This flag bus is capable of High-Impedance state, this is important during expansion of
multi-queue devices. During direct operation the PAFn bus is updated to show the PAF status of a queues
within a selected device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled
operation the PAFn bus is loaded with the PAF status of multi-queue flow-control devices sequentially
based on the rising edge of WCLK.
A Partial Reset can be performed on a single queue selected within the multi-queue device. Before a Partial
Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking PRS LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
These are the 18 data output pins. Data is read out of the device via these output pins on the rising edge
all outputs may be used, any unused outputs should not be connected.
The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR.
Note, that a read queue selection cannot be made, (RADEN must NOT go active) until programming of
the part has been completed and SENO has gone LOW.
When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output bus
Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK while
RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the device
to be placed on the PAEn bus during direct flag operation. During polled flag operation the PAEn bus is
cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The PAE and OV outputs
are all synchronized to RCLK. During device expansion the EXO and EXI signals are based on RCLK.
RCLK must be continuous and free-running.
For the 4Q device the RDADD bus is 6 bits. The RDADD bus is a dual purpose address bus. The first
function of RDADD is to select a queue to be read from. The least significant 2 bits of the bus, RDADD[1:0]
are used to address 1 of 4 possible queues within a multi-queue device. Address pin, RDADD[2] provides
the user with a Null-Q address. If the user does not wish to address one of the 4 queues, a Null-Q can
be addressed using this pin. The Null-Q operation is discussed in more detail later. The most significant
3 bits, RDADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in
expansion mode. These 3 MSB’s will address a device with the matching ID code. The address present
8
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES