IDT72V51233L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51233L7-5BB8 Datasheet - Page 38

• Manufacturer Part Number: IDT72V51233L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51233L7-5BB8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51233L7-5BB8

Cycle:
*A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* Word, Wd-m is written into Q2 causing the PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + t
*D* Queue 0 if device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 2 WCLK + t
*E* The PAF flag goes LOW based on the write 2 cycles earlier.
*F* The PAF flag goes HIGH due to the queue switch to Q0.
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK
WEN
RCLK
WRADD
WADEN
PAF
(Device 1)
PAF
(Device 2)
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + t
De-assertion: t
If t
PAF
REN
WCLK
SKEW2
WEN
Din
t
is violated there will be one extra WCLK cycle.
CLKL
SKEW2
HIGH-Z
t
AS
t
QS
+ WCLK + t
WAF
D
t
1
*A*
ENS
Q
2
WAF
t
QH
t
AH
D - (m+1) words in Queue
t
CLKL
t
ENH
*B*
Figure 18. Almost Full Flag Timing and Queue Switch
D
1
t
1
ENS
Q
t
Figure 19. Almost Full Flag Timing
DS
2
W
*C*
D-m
t
t
t
FFHZ
ENH
DH
2
t
AFLZ
t
38
WAF
t
t
AS
QS
D
t
1
*D*
ENS
Q
1
0
t
t
QH
SKEW2
t
AH
t
ENH
D - m words in Queue
*E*
WAF
2
.
t
WAF
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
*F*
WAF
1
latency.
t
WAF
t
WAF
D-(m+1) words
in Queue
5941 drw20
5941 drw21