IDT72V51233L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51233L7-5BB8 Datasheet - Page 23

• Manufacturer Part Number: IDT72V51233L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51233L7-5BB8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51233L7-5BB8

NOTE:
n = Almost Empty Offset value.
PAE Timing
Assertion:
De-assertion: Write to PAE HIGH: t
NOTE:
D = Queue Depth
m = Almost Full Offset value.
PAF Timing
Assertion:
De-assertion: Read to PAF HIGH: t
PAFn Timing
Assertion:
De-assertion: Read to PAFn HIGH: t
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
In18 to out18 or In9 to out9
(Both ports selected for same queue when the 1
In18 to out18 or In9 to out9
(Write port only selected for same queue when the D-m Writes
1
In18 to out9
In9 to out18
Word is written in until the boundary is reached)
In18 to out18 or In9 to out9
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
In18 to out9
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
In9 to out18
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
st
Word is written in until the boundary is reached) (see note below for timing)
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Default values:
Default values:
Programmable Almost Empty Flag, PAE Boundary
Write Operation to PAF LOW: 2 WCLK + t
If t
Write Operation to PAFn LOW: 2 WCLK* + t
If t
Read Operation to PAE LOW: 2 RCLK + t
If t
SKEW2
SKEW3
SKEW2
I/O Set-Up
I/O Set-Up
is violated there may be 1 added clock: t
is violated there may be 1 added clock: t
is violated there may be 1 added clock: t
if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
SKEW2
SKEW2
SKEW3
+ RCLK + t
+ WCLK + t
+ WCLK* + t
st
st
st
st
RAE
WAF
PAF/PAFn Goes LOW after
D+1-m Writes
(see note below for timing)
PAF/PAFn Goes LOW after
PAF/PAFn Goes LOW after
D-m Writes (see below for timing)
PAF/PAFn Goes LOW after
(see note below for timing)
PAE Goes HIGH after n+2
Writes
(see note below for timing)
PAE Goes HIGH after n+1
Writes
(see note below for timing)
PAE Goes HIGH after
([n+2] x 2) Writes
(see note below for timing)
([D+1-m] x 2) Writes
WAF
RAE
PAF
PAF & PAFn Boundary
PAF
PAE Assertion
SKEW3
SKEW2
SKEW2
+ 2 WCLK* + t
+ 2 WCLK + t
+ 2 RCLK + t
WAF
RAE
PAF
23
NOTE:
n = Almost Empty Offset value.
PAEn Timing
Assertion:
De-assertion: Write to PAEn HIGH: t
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
In18 to out18 or In9 to out9
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
In18 to out18 or In9 to out9
(Write port only selected for same queue when the n+1 Writes
1
In18 to out9
In9 to out18
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
In9 to out18
(Write port only selected for same queue when the ([n+1] x 2) Writes
1
st
st
Word is written in until the boundary is reached) (see note below for timing)
Word is written in until the boundary is reached) (see note below for timing)
Programmable Almost Empty Flag Bus, PAEn Boundary
Default values: if DF is LOW at Master Reset then n = 8
Read Operation to PAEn LOW: 2 RCLK* + t
If t
SKEW3
I/O Set-Up
is violated there may be 1 added clock: t
if DF is HIGH at Master Reset then n = 128
SKEW3
COMMERCIAL AND INDUSTRIAL
+ RCLK* + t
st
st
TEMPERATURE RANGES
PAEn Boundary Condition
(see note below for timing)
(see note below for timing)
PAEn Goes HIGH after
n+2 Writes
PAEn Goes HIGH after
PAEn Goes HIGH after n+1
Writes (see below for timing)
PAEn Goes HIGH after
([n+2] x 2) Writes
PAEn Goes HIGH after
PAE
PAE
SKEW3
+ 2 RCLK* + t
PAE