IDT89HPES8T5ZHBCG IDT, Integrated Device Technology Inc, IDT89HPES8T5ZHBCG Datasheet - Page 3

• Manufacturer Part Number: IDT89HPES8T5ZHBCG
• Description: IC PCI SW 8LANE 5PORT 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES8T5ZHBCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES8T5ZHBCG

SMBus Interface
configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of
the PES8T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an
external Hot-Plug I/O expander.
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
4(a), the master and slave SMBuses are tied together and the PES8T5 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES8T5 registers supports SMBus arbitration. In some systems, this SMBus master
interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support
these systems, the PES8T5 may be configured to operate in a split configuration as shown in Figure 4(b).
The PES8T5 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the
serial EEPROM.
IDT 89HPES8T5 Data Sheet
The PES8T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES8T5, allowing every
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
As shown in Figure 4, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
Bit
Table 1 Master and Slave SMBus Address Assignment
1
2
3
4
5
6
7
Figure 3 Configuration Option
x1
x1
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
SSMBADDR[5]
Address
SMBus
Slave
x1
x1
PES8T5
PES8T5
3 of 31
0
1
1
x4
x4
x1
x1
x1
x1
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
Address
Master
SMBus
1
0
1
March 27, 2008