IDT89HPES8T5ZHBCG IDT, Integrated Device Technology Inc, IDT89HPES8T5ZHBCG Datasheet

no-image

IDT89HPES8T5ZHBCG

Manufacturer Part Number
IDT89HPES8T5ZHBCG
Description
IC PCI SW 8LANE 5PORT 324-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT89HPES8T5ZHBCG

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
89HPES8T5ZHBCG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT89HPES8T5ZHBCG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Device Overview
Express switching solutions. The PES8T5 is an 8-lane, 5-port peripheral
chip that performs PCI Express packet switching with a feature set opti-
mized for high performance applications such as servers, storage and
communications/networking. It provides connectivity and switching func-
tions between a PCI Express upstream port and up to four downstream
ports and supports switching between downstream ports.
Features
Block Diagram
© 2008 Integrated Device Technology, Inc.
The 89HPES8T5 is a member of the IDT PRECISE™ family of PCI
High Performance PCI Express Switch
Flexible Architecture with Numerous Configuration Options
– Eight 2.5 Gbps PCI Express lanes
– Five switch ports
– Upstream port is x4
– Downstream ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
Transaction Layer
Data Link Layer
Mux / Demux
(Port 0)
SerDes
Logical
Layer
Phy
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
Transaction Layer
Data Link Layer
Mux / Demux
(Port 2)
SerDes
Logical
8-Lane 5-Port
PCI Express® Switch
Layer
Phy
5-Port Switch Core / 8 PCI Express Lanes
Route Table
Figure 1 Internal Block Diagram
Transaction Layer
1 of 31
Data Link Layer
Mux / Demux
(Port 3)
SerDes
Logical
Layer
Phy
Legacy Support
– PCI compatible INTx emulation
– Bus locking
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates eight 2.5 Gbps embedded SerDes with 8B/10B
Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
Power Management
– Utilizes advanced low-power design techniques to achieve low
– Supports PCI Power Management Interface specification
– Unused SerDes are disabled
Arbitration
Port
• Supports device power management states: D0, D3
queueing
encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
server motherboards
typical power consumption
(PCI-PM 1.1)
D3
cold
Transaction Layer
Data Link Layer
Mux / Demux
(Port 4)
SerDes
Logical
Layer
Phy
Scheduler
Transaction Layer
Data Link Layer
Mux / Demux
89HPES8T5
(Port 5)
SerDes
Data Sheet
Logical
Layer
March 27, 2008
Phy
hot
and

Related parts for IDT89HPES8T5ZHBCG

IDT89HPES8T5ZHBCG Summary of contents

Page 1

Device Overview The 89HPES8T5 is a member of the IDT PRECISE™ family of PCI Express switching solutions. The PES8T5 is an 8-lane, 5-port peripheral chip that performs PCI Express packet switching with a feature set opti- mized for high ...

Page 2

IDT 89HPES8T5 Data Sheet ◆ Testability and Debug Features – Ability to read and write any internal register via the SMBus Eleven General Purpose Input/Output pins ◆ – Each pin may be individually configured as an input or output – ...

Page 3

IDT 89HPES8T5 Data Sheet SMBus Interface The PES8T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES8T5, allowing every configuration register in the device to be read or written by an external ...

Page 4

IDT 89HPES8T5 Data Sheet Processor SMBus PES8T5 SSMBCLK SSMBDAT MSMBCLK MSMBDAT (a) Unified Configuration and Management Bus Hot-Plug Interface The PES8T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the ...

Page 5

IDT 89HPES8T5 Data Sheet Signal PE4RP[0] PE4RN[0] PE4TP[0] PE4TN[0] PE5RP[0] PE5RN[0] PE5TP[0] PE5TN[0] PEREFCLKP[2:1] PEREFCLKN[2:1] REFCLKM Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Type Name/Description I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pair for port ...

Page 6

IDT 89HPES8T5 Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function ...

Page 7

IDT 89HPES8T5 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Type Name/Description I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between ...

Page 8

IDT 89HPES8T5 Data Sheet Signal V CORE APE Type Name/Description I Core VDD. Power supply for core logic. I I/O VDD. LVTTL I/O buffer power supply. ...

Page 9

IDT 89HPES8T5 Data Sheet Pin Characteristics Note: Some input pads of the PES8T5 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if ...

Page 10

IDT 89HPES8T5 Data Sheet Function System Pins CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 1. Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. 2. ...

Page 11

IDT 89HPES8T5 Data Sheet Logic Diagram — PES8T5 Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 3 PCI Express Switch SerDes Input Port 4 PCI Express ...

Page 12

IDT 89HPES8T5 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter PEREFCLK Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of ...

Page 13

IDT 89HPES8T5 Data Sheet 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal GPIO 1 GPIO[10:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width ...

Page 14

IDT 89HPES8T5 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express ...

Page 15

IDT 89HPES8T5 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured ...

Page 16

IDT 89HPES8T5 Data Sheet Heat Sink Table 17 lists heat sink requirements for the PES8T5 under two common usage scenarios. As shown in this table, a heat sink is not required in most cases. . Air Flow Zero 1 m/S ...

Page 17

IDT 89HPES8T5 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V ...

Page 18

IDT 89HPES8T5 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN ...

Page 19

IDT 89HPES8T5 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES8T5 The following table lists the pin numbers and signal names for the PES8T5 device. Pin Function Alt Pin A1 V B17 B18 SS A3 PE0RP03 ...

Page 20

IDT 89HPES8T5 Data Sheet Pin Function Alt Pin H11 V K12 SS H12 V CORE K13 DD H13 V K14 SS H14 V IO K15 DD H15 V CORE K16 DD H16 GPIO_07 1 K17 H17 GPIO_06 K18 H18 GPIO_05 ...

Page 21

IDT 89HPES8T5 Data Sheet Pin Function Alt Pin T15 MSMBSMODE U7 T16 V APE U8 DD T17 T18 V CORE U10 DD U1 PE3TP00 U11 U2 PE3TN00 U12 U13 U14 SS ...

Page 22

IDT 89HPES8T5 Data Sheet Power Pins V Core V Core F10 A6 F15 A8 G12 A10 H4 A12 H7 A14 H9 A15 H10 B17 H12 B18 H15 C4 J6 C13 J9 C16 J10 D4 J13 D14 K1 ...

Page 23

IDT 89HPES8T5 Data Sheet Ground Pins A17 A18 B10 B12 B14 B15 C11 D11 D13 E11 E13 ...

Page 24

IDT 89HPES8T5 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 PE0RP01 ...

Page 25

IDT 89HPES8T5 Data Sheet Signal Name PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 PE4RN00 PE4RP00 PE4TN00 PE4TP00 PE5RN00 PE5RP00 PE5TN00 PE5TP00 PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 ...

Page 26

IDT 89HPES8T5 Data Sheet Signal Name SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location I D17 I D16 I E15 I E16 See Table ...

Page 27

IDT 89HPES8T5 Data Sheet PES8T5 Pinout — Top View Core (Power ...

Page 28

IDT 89HPES8T5 Data Sheet PES8T5 Package Drawing — 324-Pin BC324/BCG324 March 27, 2008 ...

Page 29

IDT 89HPES8T5 Data Sheet PES8T5 Package Drawing — Page Two March 27, 2008 ...

Page 30

IDT 89HPES8T5 Data Sheet Revision History February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Changed device revision in Ordering Information from ZD to ZH. November 14, 2007: Added new ...

Page 31

IDT 89HPES8T5 Data Sheet Ordering Information A AAA NN Product Operating Device Family Voltage Family Valid Combinations 89HPES8T5ZHBC 324-pin BC324 package, Commercial Temperature 89HPES8T5ZHBCG 324-pin Green BCG324 package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA ...

Related keywords