LTC3832-1ES8#TR Linear Technology, LTC3832-1ES8#TR Datasheet - Page 7

• Manufacturer Part Number: LTC3832-1ES8#TR
• Description: IC CTRLR DC/DC SYNC BUCK 8-SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC3832-1ES8#TR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 2.5V
• Current - Output: 20A
• Frequency - Switching: 300kHz
• Voltage - Input: 3 ~ 8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

BLOCK DIAGRA
FREQSET (Pin 11/NA): Frequency Set. Use this pin to
adjust the free-running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 300kHz.
A resistor from FREQSET to ground speeds up the oscil-
lator; a resistor to V
I
the threshold for the internal current limit comparator. If
I
current limit. I
Connect this pin to the main V
through an external resistor to set the current limit thresh-
old. Connect a 0.1 F decoupling capacitor across this
resistor to filter switching noise.
I
the switching node at the source of Q1 and the drain of Q2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging I
sensing the voltage drop across the upper N-channel
MOSFET, Q1.
PI FU CTIO S
MAX
FB
FB
U
drops below I
(Pin 13/NA): Current Limit Sense. Connect this pin to
(Pin 12/NA): Current Limit Threshold Set. I
U
MAX
MAX
has an internal 12 A pull-down to GND.
FREQSET
CC
U
COMP
SHDN
with G1 on, the LTC3832 goes into
SS
slows it down.
W
QC
IN
supply at the drain of Q1,
(LTC3832)
12 A
100 s DELAY
OSCILLATOR
INTERNAL
FB
2.2V
1.2V
QSS
.This pin is used for
V
+
REF
ERR
CC
DISABLE
I
THERMAL SHUTDOWN
LIM
–
–
+
MAX
LOGIC AND
–
+
PWM
V
sets
12 A
+
–
POWER DOWN
I
I
FB
MAX
V
PV
V
REF
CC
CC1
V
internal circuits draw their supply from this pin. Connect
this pin to a clean power supply, separate from the main
V
bypass capacitor. The LTC3832-1has V
together at Pin 7 and requires a 10 F bypass capacitor to
GND.
PV
this pin to the main high power supply.
G2 (Pin 16/Pin 8): Bottom Gate Driver Output. Connect
this pin to the gate of the lower N-channel MOSFET, Q2.
This output swings from PGND to PV
when G1 is high or during shutdown mode. To prevent
output undershoot during a soft-start cycle, G2 is held low
until G1 first goes high (FFBG in the Block Diagram).
+ 2.5V
–
+ 10%
CC
IN
MAX
CC2
DISABLE GATE DRIVE
supply at the drain of Q1. This pin requires a 4.7 F
(Pin 14/Pin 7): Power Supply Input. All low power
+
(Pin 15/Pin 7): Power Supply Input for G2. Connect
POR
S
R
S
R
FFBG
V
REF
Q
Q
Q
+ 10%
V
REF
5.7k
ENABLE
G2
LTC3832/LTC3832-1
18k
BG
3832 BD
PV
G1
PV
G2
PGND
V
GND
FB
SENSE
SENSE
CC
CC1
CC2
CC2
+
–
CC
. It remains low
and PV
sn3832 3832fs
CC2
7
tied