LTC1875EGN Linear Technology, LTC1875EGN Datasheet - Page 12

• Manufacturer Part Number: LTC1875EGN
• Description: IC REG STEP-DWN SYNC 1.5A 16SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1875EGN

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 6 V
• Current - Output: 1.5A
• Frequency - Switching: 550kHz
• Voltage - Input: 2.65 ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
Phase-Locked Loop and Frequency Synchronization
The LTC1875 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the MOSFET turn-on to be locked to the rising edge
of an external frequency source. The frequency range of
the voltage-controlled oscillator is 350kHz to 750kHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector will not
lock up on input frequencies close to the harmonics of the
VCO center frequency. The PLL hold-in range f
to the capture range, f
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
LTC1875
12
Figure 5. Relationship Between Oscillator Frequency
and Voltage at PLL_LPF Pin
Figure 4. Setting the LTC1875 Output Voltage
1000
900
800
700
600
500
400
300
200
100
0
0
U
LTC1875
0.5
H
SGND
V
= f
U
FB
V
PLLLPF
0.8V V
C
1
= 200kHz.
(V)
OUT
W
R1
R2
1875 F04
1.5
6V
1875 F05
2
U
H
is equal
filter network on the PLL_LPF pin. The relationship be-
tween the voltage on the PLL_LPF pin and operating
frequency is shown in Figure 5. A simplified block diagram
is shown in Figure 6.
If the external frequency (V
550kHz, the center frequency, current is sourced continu-
ously, pulling up the PLL_LPF pin. When the external
frequency is less than 550kHz, current is sunk continu-
ously, pulling down the PLL_LPF pin. If the external and
internal frequencies are the same but exhibit a phase
difference, the current sources turn on for an amount of
time corresponding to the phase difference. Thus the
voltage on the PLL_LPF pin is adjusted until the phase and
frequency of the external and internal oscillators are
identical. At this stable operating point the phase com-
parator output is open and the filter capacitor C
voltage.
The loop filter components C
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
acquires lock. Typically R
0.01 F. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillation frequency by a DC
voltage on the V
SYNC/
MODE
Figure 6. Phase-Locked Loop Block Diagram
FREQUENCY
DETECTOR
DIGITAL
PHASE/
LP
PLLLPF
and R
2.4V
pin.
LP
LP
determine how fast the loop
= 10k and C
SYNC/MODE
LP
and R
LP
PLL_LPF
) is greater than
smooth out the
LP
VCO
R
LP
is 2200pF to
LP
holds the
C
1875 F06
LP
1875f