LTC3703EGN-5 Linear Technology, LTC3703EGN-5 Datasheet - Page 25

• Manufacturer Part Number: LTC3703EGN-5
• Description: IC BUCK/BOOST SYNC ADJ 5A 16SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck), Step-Up (Boost)r

Specifications of LTC3703EGN-5

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 55.8 V
• Current - Output: 5A
• Frequency - Switching: 100kHz ~ 600kHz
• Voltage - Input: 9.3 ~ 60 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
MODE/SYNC Pin (External Synchronization)
The internal LTC3703-5 oscillator can be synchronized to
an external oscillator by applying and clocking the MODE/
SYNC pin with a signal above 2V
locks to the external clock after the second clock transi-
tion is received. When external synchronization is de-
tected, LTC3703-5 will operate in forced continuous
mode. If an external clock transition is not detected for
three successive periods, the internal oscillator will revert
to the frequency programmed by the R
internal oscillator can synchronize to frequencies be-
tween 100kHz and 600kHz, independent of the frequency
programmed by the R
mended that an R
frequency programmed by the R
expected frequency of the external clock. In this way, the
best converter operation (ripple, component stress, etc)
is achieved if the external clock signal is lost.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time t
that the LTC3703-5 is capable of turning the top MOSFET
on and off again. It is determined by internal timing delays
and the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
where t
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3703-5 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
t
Pin Clearance/Creepage Considerations
The LTC3703-5 is available in two packages (GN16 and
G28) both with identical functionality. The GN16 package
gives the smallest size solution, however the 0.013”
(minimum) space between pins may not provide sufficient
ON(MIN)
t
ON
=
ON(MIN)
for the same step-down ratio.
V
V
IN
OUT
•
f
is typically 200ns.
>
t
SET
ON MIN
ON(MIN)
U
(
SET
resistor be chosen such that the
)
resistor. However, it is recom-
U
is the smallest amount of time
P-P
SET
. The internal oscillator
resistor is close to the
W
SET
resistor. The
U
PC board trace clearance between high and low voltage
pins in higher voltage applications. Where clearance is an
issue, the G28 package should be used. The G28 package
has 4 unconnected pins between the all adjacent high
voltage and low voltage pins, providing 5(0.0106”) =
0.053” clearance which will be sufficient for most applica-
tions up to 60V. For more information, refer to the printed
circuit board design standards described in IPC-2221
(www.ipc.org).
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (x100%). Per-
cent efficiency can be expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement. Al-
though all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703-5 circuits: 1) LTC3703-5 V
2) MOSFET gate current, 3) I
MOSFET transition losses.
1. V
current given in the Electrical Characteristics table which
powers the internal control circuitry of the LTC3703-5.
Total supply current is typically about 2.5mA and usually
results in a small (<1%) loss which is proportional to V
2. DRV
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched on and
then off, a packet of gate charge Q
ground. The resulting dQ/dt is a current out of the DRV
supply. In continuous mode, I
where Q
and bottom MOSFETs.
3. I
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
%Efficiency = 100% – (L1 + L2 + L3 + ...)
2
CC
R losses are predicted from the DC resistances of
Supply current. The V
CC
G(TOP)
current is MOSFET driver current. This current
and Q
G(BOT)
are the gate charges of the top
DRVCC
CC
2
R losses and 4) Topside
current is the DC supply
G
moves from DRV
= f(Q
LTC3703-5
G(TOP)
CC
+ Q
current,
G(BOT)
25
37035fa
CC
CC
CC
to
),
.