ISL6263ACRZ Intersil, ISL6263ACRZ Datasheet - Page 14

• Manufacturer Part Number: ISL6263ACRZ
• Description: IC VREG 5BIT 1PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6263ACRZ

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 5 ~ 25 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the drive voltage at the end of a PWM cycle is 200mV. One
will find that a bootstrap capacitance of at least 0.125µF is
required. The next larger standard value capacitance is
0.15µF. A good quality ceramic capacitor is recommended.
Soft-Start and Soft Dynamic VID Slew Rates
The output voltage of the converter tracks V
voltage across the SOFT and VSS pins. Shown in Figure 1,
the SOFT pin is connected to the output of the VID DAC
through the unidirectional soft-start current source I
bidirectional soft-dynamic VID current source I
non-inverting input of the error amplifier. Current is sourced
from the SOFT pin when I
both source and sink current when I
soft-start capacitor C
proportional to I
selects I
current through the output capacitors is maintained below
the OCP threshold. Once soft-start has completed, I
automatically selected for output voltage changes
commanded by the VID inputs, charging C
output voltage is commanded to rise, and discharging
C
The IMVP-6+ Render Voltage Regulator specification
requires a minimum of 10mV/µs for SLEWRATE
value for C
10mV/µs when the soft-dynamic VID current source I
the minimum specified value in the “Electrical Specifications”
table on page 8. The value of C
Equation 4:
Choosing the next lower standard component value of
0.015µF will guarantee 10mV/µs SLEWRATE
choice of C
should expect the output voltage during soft-start to slew to
the voltage commanded by the VID settings at a nominal
rate given by Equation 5:
Note that the slewrate is the average rate of change
between the initial and final voltage values.
RBIAS Current Reference
The RBIAS pin is internally connected to a 1.545V reference
through a 3kΩ resistance. A bias current is established by
connecting a ±1% tolerance, 150kΩ resistor between the
RBIAS and VSS pins. This bias current is mirrored, creating the
reference current I
Do not connect any other components to this pin, as they will
have a negative impact on the performance of the IC.
C
dV
---------------------- -
SOFT
SOFT
SOFT
dt
when the output voltage is commanded to fall.
=
SS
=
I
------------------------ -
⎛
⎝
DVIDmin
------------------ -
C
SOFT
10mV
--------------- -
SOFT
for the soft-start sequence so that the inrush
SOFT
I
μs
SS
SS
⎞
⎠
must guarantee the minimum slew-rate of
controls the startup slew-rate as well. One
OCSET
=
=
or I
---------------------- -
0.015μF
180μA
----------------- -
SOFT
42μA
10k
DVID
that is sourced from the OCSET pin.
SS
changes voltage at a rate
. The ISL6263A automatically
=
≈
14
is active. The SOFT pin can
0.018μF
2.8mV
----------------- -
SOFT
μs
DVID
, can be calculated from
is active. The
SOFT
SOFT,
GFX
DVID
GFX
when the
. This
the
SS
, and the
DVID
. The
DVID
(EQ. 4)
or the
(EQ. 5)
is
ISL6263A
is
Setting the PWM Switching Frequency
The R
architecture, lacking a fixed-frequency clock signal to
produce PWM. The switching frequency increases during
the application of a load to improve transient performance.
The static PWM frequency varies slightly depending on the
input voltage, output voltage, and output current, but this
variation is normally less than 10% in continuous conduction
mode.
Refer to Figure 2 and find that resistor R
between the V W and COMP pins. A current is sourced from
VW through R
voltage signal V
frequency. The relationship between the resistance of R
and the switching frequency in CCM is approximated by
Equation 6:
For example, the value of R
approximately:
This relationship only applies to operation in constant
conduction mode because the PWM frequency naturally
decreases as the load decreases while in diode emulation
mode.
Static Droop Design Using DCR Sensing
The ISL6263A has an internal differential amplifier to
accurately regulate the voltage at the processor die.
For DCR sensing, the process to compensate the DCR
resistance variation takes several iterative steps. Figure 2
shows the DCR sensing method. Figure 8 shows the
simplified model of the droop circuitry. The inductor DC
current generates a DC voltage drop on the inductor DCR.
Equation 8 gives this relationship:
An R-C network senses the voltage across the inductor to
get the inductor current information. R
NTC network consisting of R
choice of R
The first step in droop load line compensation is to adjust
R
appears even at light loads between the VSUM and VO pins.
As a rule of thumb, the voltage drop V
network, is set to be 0.3x to 0.8x V
G
which to derive the droop voltage.
R
7.1
V
DCR
NTCEQ
FSET
1
, provides a reasonable amount of light load signal from
×10
3
3
=
=
modulator scheme is not a fixed-frequency
=
, and R
I
o
(
-----------------------------------------
(
--------------------------------------------------------------------
T 0.5
⋅
3.33 10
S
400
DCR
–
will be discussed in the following section.
FSET
×
×
W
S
400
10
×
such that the correct droop voltage
which determines the PWM switching
10
–
–
creating the synthetic ripple window
12
6
×
–
6
–
10
)
0.5
–
12
×
FSET
10
NTC
–
6
)
, R
for 300kHz operation is
DCR
NTCS, and
NTCEQ
N
. This gain, defined as
FSET
across the R
is connected
represents the
R
NTCP
July 8, 2010
NTCEQ
. The
(EQ. 6)
(EQ. 7)
FN9284.3
(EQ. 8)
FSET