ISL6263ACRZ Intersil, ISL6263ACRZ Datasheet - Page 13

• Manufacturer Part Number: ISL6263ACRZ
• Description: IC VREG 5BIT 1PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6263ACRZ

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 5 ~ 25 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overcurrent
Short Circuit
Overvoltage
(+195mV)
between VO pin
and SOFT pin
Severe
Overvoltage
(+1.55V)
between VO pin
and VSS pin
Undervoltage
(-300mV)
between VO pin
and SOFT pin
FAULT TYPE
UGATE
LGATE
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263A
PWM
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
FIGURE 6. GATE DRIVER TIMING DIAGRAM
0.0
20nC
t
PDRU
VOLTAGE
0.1
PROTECTION
Immediately UGATE, and
DURATION
PRIOR TO
Q
0.2
FAULT
GATE
120µs
<2µs
1ms
1ms
0.3
= 100nC
ΔV
t
0.4
PDRL
BOOT_CAP
13
LGATE, UGATE, and
PGOOD latched low
LGATE, UGATE, and
PGOOD latched low
LGATE, UGATE, and
PGOOD latched low
PGOOD latched low,
LGATE toggles ON
when VO >1.55V
OFF when
VO <0.77V
until fault reset
LGATE, UGATE, and
PGOOD latched low
0.5
PROTECTION
ACTIONS
0.6
(V)
0.7
0.8
0.9
Cycle
VR_ON or
VDD
Cycle
VR_ON or
VDD
Cycle
VR_ON or
VDD
Cycle
VDD only
Cycle
VR_ON or
VDD
RESET
FAULT
1.0
1V
1V
ISL6263A
A severe overvoltage protection fault occurs immediately
after the voltage between the VO and VSS pins exceed the
rising severe-overvoltage threshold V
the same reference voltage used by the VID DAC. The
ISL6263A will latch UGATE and PGOOD low but unlike other
protective faults, LGATE remains high until the voltage
between VO and VSS falls below approximately 0.77V, at
which time LGATE is pulled low. The LGATE pin will continue
to switch high and low at 1.545V and 0.77V until VDD has
gone below the falling POR threshold voltage
This provides maximum protection against a shorted
high-side MOSFET while preventing the output voltage from
ringing below ground. The severe-overvoltage fault circuit
can be triggered after another fault has already been
latched.
Gate-Driver Outputs LGATE and UGATE
The ISL6263A has internal high-side and low-side
N-Channel MOSFET gate-drivers. The LGATE driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant. The LGATE
pull-down resistance is very low in order to clamp the
gate-source voltage of the MOSFET below the V
turnoff. The current transient through the low-side gate at
turnoff can be considerable due to the characteristic large
switching charge of a low r
Adaptive shoot-through protection prevents the gate-driver
outputs from going high until the opposite gate-driver output
has fallen below approximately 1V. The UGATE turn-on
propagation delay t
delay t
on page 7. The power for the LGATE gate-driver is sourced
directly from the PVCC pin. The power for the UGATE
gate-driver is sourced from a boot-strap capacitor connected
across the BOOT and PHASE pins. The boot capacitor is
charged from PVCC through an internal boot-strap diode
each time the low-side MOSFET turns on, pulling the
PHASE pin low.
Internal Bootstrap Diode
The ISL6263A has an integrated boot-strap Schottky diode
connected from the PVCC pin to the BOOT pin. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
The minimum value of the bootstrap capacitor can be
calculated from Equation 3:
where Q
charge the gate of the upper MOSFET. The ΔV
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q
C
BOOT
PDRL
≥
GATE
----------------------- -
ΔV
GATE
Q
GATE
BOOT
are found in the “Electrical Specifications” table
is the amount of gate charge required to fully
, of 25nC at 5V and also assume the droop in
PDRU
and LGATE turn-on propagation
DS(ON)
MOSFET.
OVPS
, which is 1.545V,
V
BOOT
VDD_THF.
GS(th)
July 8, 2010
term is
FN9284.3
(EQ. 3)
at