ISL6721ABZ Intersil, ISL6721ABZ Datasheet - Page 11

• Manufacturer Part Number: ISL6721ABZ
• Description: IC CTRLR PWM SGL ENDED 16-SOIC
• Manufacturer: Intersil

Specifications of ISL6721ABZ

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 100%
• Voltage - Supply: 9 V ~ 18 V
• Buck: Yes
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 1MHz
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The minimum amount of capacitance to place at the SLOPE
pin is calculated in Equation 6:
where t
voltage to be added as slope compensation to the current
feedback signal. In general, the amount of slope
compensation added is 2 to 3 times the minimum required.
Example:
Assume the inductor current signal presented at the ISENSE
pin decreases 125mV during the Off period, and:
Switching Frequency, f
Duty Cycle, D = 60%
t
t
Determine the downslope:
Downslope = 0.125V/1.6µs = 78mV/µs. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time.
V
Therefore,
C
An appropriate slope compensation capacitance for this
example would be 1/2 to 1/3 the calculated value, or
between 68pF and 33pF.
Overvoltage and Undervoltage Monitor
The OV and UV signals are inputs to a window comparator
used to monitor the input voltage level to the converter. If the
voltage falls outside of the user designated operating range,
a shutdown fault occurs. For OV faults, the supply current,
I
is attempted. If the fault is cleared, a soft-start cycle begins.
Otherwise another shutdown cycle occurs. A UV condition
also results in a shutdown fault, but the device does not
enter the low power mode and no restart delay occurs when
the fault clears.
C
ON
OFF
CC
SLOPE
SLOPE MIN
SLOPE
, is reduced to 200µA for ~295ms at which time recovery
= D/f
= (1 - D)/fsw = 1.6µs
ON
CURRENT SENSE SIGNAL
(
=
=
sw
Current Sense Signal
1
-- - 0.078 2.4
2
is the On time and V
4.24
= 0.6/250E3 = 2.4µs
)
•
=
×10
4.24
–
6
•
×10
•
---------------------- -
V
sw
–
SLOPE
6
t
=
FIGURE 5.
ON
•
= 250kHz
94mV
2.4
-----------------------
0.094
11
Time
TIME
×10
SLOPE
DOWNSLOPE
–
Downslope
6
F
≈
110pF
is the amount of
(EQ. 6)
(EQ. 7)
(EQ. 8)
ISL6721
A resistor divider between V
determines the operational thresholds. The UV threshold
has a fixed hysteresis of 75mV nominal.
Overcurrent Operation
The overcurrent threshold level is set by the voltage applied
at the ISET pin. Setting the overcurrent level may be
accomplished by using a resistor divider network from VREF
to LGND. The ISET threshold should be set at a level that
corresponds to the desired peak output inductor current plus
the additive effects of slope compensation.
Overcurrent delayed shutdown is enabled once the soft-start
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the
discharging current source is enabled. The soft-start
capacitor is discharged at a rate of 40µA. At the same time,
a 50µs retriggerable one-shot timer is activated amd it
remains active for 50µs after the overcurrent condition stops.
The soft-start discharge cycle cannot be reset until the one-
shot timer becomes inactive. If the soft-start capacitor
discharges by more than 0.125V to 4.375V, the output is
disabled and the soft-start capacitor is discharged. The
output remains disabled and I
approximately 295ms. A new soft-start cycle is then initiated.
The shutdown and restart behavior of the OC protection is
often referred to as hic-cup operation due to its repetitive
start-up and shutdown characteristic.
If the overcurrent condition ceases at least 50µs prior to the
soft-start voltage reaching 4.375V, the soft-start charging
and discharging currents revert to normal operation and the
soft-start voltage is allowed to recover.
Hiccup OC protection may be defeated by setting ISET to a
voltage that exceeds the Error Amplifier current control
voltage, or about 1.5V.
Leading Edge Blanking
The initial 100ns of the current feedback signal input at
ISENSE is removed by the leading edge blanking circuitry.
The blanking period begins when the GATE output leading
edge exceeds 3.0V. Leading edge blanking prevents current
spikes from parasitic elements in the power supply from
causing false trips of the PWM comparator and the
overcurrent comparator.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V, the OV
input exceeds 2.50V, the UV input falls below 1.45V, or the
junction temperature of the die exceeds ~+130°C. When a
Fault is detected the GATE output is disabled and the
soft-start capacitor is quickly discharged. When the Fault
condition clears and the soft-start voltage is below the reset
threshold, a soft-start cycle begins.
IN
CC
and LGND to each input
drops to 200µA for
March 5, 2008
FN9110.6