ISL8118IRZ Intersil, ISL8118IRZ Datasheet - Page 19

• Manufacturer Part Number: ISL8118IRZ
• Description: IC CTRLR PWM 1-PHASE 28-QFN
• Manufacturer: Intersil

Specifications of ISL8118IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 2.97 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
for the input capacitor of a buck regulator is approximated in
the following.
I
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The ISL8118 requires 2 N-Channel power MOSFETs. These
should be selected based upon rDS(ON), gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
IN RMS
IN RMS
FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR
,
,
OR
0.6
0.5
0.4
0.3
0.2
0.1
0.0
=
=
0
K
I
ICM
2
O
0.1
SINGLE-PHASE BUCK CONVERTER
(
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
D D
•
–
0.2
I
O
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
2
)
0.3
+
For information regarding Intersil Corporation and its products, see www.intersil.com
I Δ
------- - D
12
DUTY CYCLE (D)
0.4
2
19
0.5
0.6
0.25Io
0.7
D
DI = 0Io
=
0.8
----------
VIN
V
0.5Io
O
0.9
(EQ. 27)
1.0
ISL8118
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the top and the bottom MOSFETs. These
losses are distributed between the two MOSFETs according
to duty factor (see the following equations). The upper
MOSFET exhibits turn-on and turn-off switching losses as
well as the reverse recover loss, while the synchronous
rectifier exhibits body-diode conduction losses during the
leading and trailing edge dead times.
where D is the duty cycle = V
recover charge; t
time, and t
These equations do not include the gate-charge losses that
are proportional to the total gate charge and the switching
frequency and partially dissipated by the internal gate
resistance of the MOSFETs. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
ISL8118 DC/DC Converter Application Circuit
Detailed information on the application circuit, including a
complete Bill of Materials and circuit board description, can
be found in application note AN1204. See Intersil’s home
page on the web: http://www.intersil.com.
P
P
P
P
P
BOTTOM
TOP
SW
DEAD
Qrr
=
=
=
Q
=
⎛
⎝
⎛
⎝
rr
I
I
ON
O
O
=
⎛
⎝
•
2
I
+
VIN F
O
⎛
⎝
+
I
----- -
12
& t
I Δ
O
+
I Δ
------- -
12
2
⎞
⎠
DL
----- -
12
I Δ
OFF
2
•
+
•
⎞
⎠
⎞
⎠
and t
t
I Δ
------- -
•
12
OFF
S
•
r
---------------------------
2
are the switching intervals.
V
DS ON
⎞
⎠
DT
•
DT
+
(
N
r
------------------------- -
⎛
⎝
DS ON
T
•
I
are leading and trailing edge dead
O
t
),T
N
DT
(
O
–
B
----- -
12
/ VIN; Q
•
I Δ
+
)B
D
⎛
⎝
⎞
⎠
I
+
O
•
•
P
t
(
–
ON
1 D
SW
----- -
12
I Δ
–
rr
⎞
⎠
is the reverse
+
•
•
)
VIN F
P
+
V
Qrr
DB
P
DEAD
•
•
t
S
DB
April 7, 2009
(EQ. 28)
(EQ. 29)
(EQ. 31)
(EQ. 32)
(EQ. 30)
•
FN6325.1
F
S