ISL8118IRZ Intersil, ISL8118IRZ Datasheet - Page 11

• Manufacturer Part Number: ISL8118IRZ
• Description: IC CTRLR PWM 1-PHASE 28-QFN
• Manufacturer: Intersil

Specifications of ISL8118IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 2.97 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OV/UV/PGOOD comparators. The VDIFF pin should be
connected to the FB pin by a standard feedback network. In
the event that the remote sense buffer is disabled, the VDIFF
pin should be connected to VOUT by a resistor divider along
with FB’s compensation network. An RC filter should be used
if VDIFF is to be connected directly to FB instead of to VOUT
through a separate resistor divider network.
GND (Bottom Side Pad, Analog Ground)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. This pin should not be left floating.
Functional Description
Initialization
The ISL8118 automatically initializes upon receipt of power
without requiring any special sequencing of the input
supplies. The Power-On Reset (POR) function continually
monitors the input supply voltages (PVCC,VFF, VCC) and
the voltage at the EN pin. Assuming the EN pin is pulled to
above ~0.50V, the POR function initiates soft-start operation
after all input supplies exceed their POR thresholds.
With all input supplies above their POR thresholds, driving
the EN pin above 0.50V initiates a soft-start cycle. In addition
to normal TTL logic, the enable pin can be used as a voltage
monitor with programmable hysteresis through the use of the
internal 10mA sink current and an external resistor divider.
This feature is especially designed for applications that have
input rails greater than a 3.3V and require specific input rail
POR and Hysteresis levels for better undervoltage
protection. Consider for a 12V application choosing
RUP = 100kΩ and RDOWN = 5.76kΩ there by setting the
rising threshold (VEN_RTH) to 10V and the falling threshold
(VEN_FTH) to 9V, for 1V of hysteresis (VEN_HYS). Care
should be taken to prevent the voltage at the EN pin from
exceeding VCC when using the programmable UVLO
functionality.
PVCC POR
VCC POR
VFF POR
FIGURE 1. SOFT-START INITIALIZATION LOGIC
HIGH = ABOVE POR; LOW = BELOW POR
EN POR
AND
11
SOFT-START
ISL8118
Soft-start
The POR function activates the internal 38µA OTA which
begins charging the external capacitor (C
target voltage of VCC. The ISL8118’s soft-start logic continues
to charge the SS pin until the voltage on COMP exceeds the
bottom of the oscillator ramp, at which point, the driver outputs
are enabled, with the bottom side MOSFET first being held low
for 200ns to provide for charging of the bootstrap capacitor.
Once the driver outputs are enabled, the OTA’s target voltage is
then changed to the margined (if margining is being used)
reference voltage (V
or down accordingly. This method reduces start-up surge
currents due to a pre-charged output by inhibiting regulator
switching until the control loop enters its linear region. By
ramping the positive input of the error amplifier to VCC and
then to V
currents from outputs that are pre-charged above the set output
voltage. As the SS pin connects directly to the non-inverting
input of the Error Amplifier, noise on this pin should be kept to a
minimum through careful routing and part placement. To
prevent noise injection into the error amplifier, the SS capacitor
should be located within 150 mils of the SS and GND pins.
Soft-start is declared done when the drivers have been enabled
and the SS pin is within ±3mV of V
Power Good
The power good comparator references the voltage on the
soft-start pin to prevent accidental tripping during margining.
The trip points are shown on Figure 3. Additionally, power
good will not be asserted until after the completion of the
soft-start cycle. A 0.1µF capacitor at the PGDLY pin will add
an additional ~7.1ms delay to the assertion of power good.
PGDLY does not delay the deassertion of power good.
R
V
R
EN_FTH
DOWN
REF_MARG
UP
R
=
DOWN
FIGURE 2. ENABLE POR CIRCUIT
R
V
------------------------- -
I
UP
VIN
=
EN_HYS
EN_HYS
=
-------------------------------------------------------- -
V
V
EN_FTH
REF_MARG
, it is even possible to mitigate surge
R
EN_RTH
UP
V
•
REF
V
–
EN_REF
–
V
I
EN_HYS
V
EN_REF
), and the SS pin is ramped up
EN_HYS
REF_MARG
= 10µA
SS
Sys_Enable
) on the SS pin to a
.
April 7, 2009
FN6325.1