ISL8118IRZ Intersil, ISL8118IRZ Datasheet - Page 17

• Manufacturer Part Number: ISL8118IRZ
• Description: IC CTRLR PWM 1-PHASE 28-QFN
• Manufacturer: Intersil

Specifications of ISL8118IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 2.97 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
G
G
G
4. Calculate R
2. Calculate C
3. Calculate C
MOD
FB
CL
A small capacitor, C
filter out noise, typically C
corresponding time constant does not reduce the overall
phase margin of the design, typically this is 2x to 10x
switching frequency of the regulator. As the ISL8118
supports 100% duty cycle, d
also uses feed-forward compensation, as such V
equal to 0.16 multiplied by the voltage at the VFF pin.
When tying VFF to V
R
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
C
C
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
R
C
f ( )
f ( )
2
1
2
3
3
f ( )
=
=
=
=
=
=
=
0.16 R
----------------------------------
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
--------------------- -
=
F
----------- - 1
--------------------------------------------------- - ⋅
s f ( ) R
------------------------------------------------------------------------------------------------------------------------ -
(
F
------------------------------------------------ -
2π R
G
1
SW
SW
1
LC
d
----------------------------- -
MOD
R
+
⋅
⋅
⋅
MAX
+
F
1
⋅
s f ( ) R
⋅
V
). F
–
s f ( ) R
P2
LC
1
2
2
2
3
3
OSC
1
such that F
f ( ) G
1
⋅
⋅
such that F
such that F
⋅
FB
1
SW
⋅
0.5 F
C
is placed below F
1
⋅
⋅
C
0.7 F
⋅
⋅
V
(
F
1
⋅
1
) and closed-loop response (G
C
1
IN
3
0
⋅
LC
⋅
2
1
represents the regulator’s switching
⋅
+
F
⋅
FB
⋅
⋅
+
C
CE
s f ( )
LC
---------------------------------------------------------------------------------------------------------- -
1
C
SW
SEN
(to adjust, change the 0.5 factor to
C
3
f ( )
IN
1
+
)
2
–
⋅
, Equation 9 simplifies to:
s f ( )
)
⋅
Z1
P1
1
⎛
⎜
⎝
Z2
(
1
R
in Figure 10, can be added to
17
where s f ( )
SEN
is placed at a fraction of the F
+
1
is placed at F
is placed at F
⋅
(
+
s f ( ) R
MAX
ESR
R
1
is chosen so the
SW
3
CE
+
,
⋅
) C
s f ( ) ESR C
⋅
equals 1. The ISL8118
+
/F
2
(typically, 0.5 to 1.0
DCR
MOD
LC
3
⋅
P2
⎛
⎜
⎝
⋅
=
-------------------- -
C
C
, the lower the F
lower in frequency
2π f j
LC
1
CE
1
LC
), feedback
) C
+
⋅
⋅
).
. Calculate C
C
⋅ ⋅
.
C
⋅
2
2
+
⎞
⎟
⎠
CL
s
⎞
⎟
⎠
2
):
f ( ) L C
(EQ. 10)
(EQ. 12)
(EQ. 13)
(EQ. 14)
(EQ. 15)
(EQ. 16)
(EQ. 17)
(EQ. 11)
OSC
⋅
LC
⋅
Z1
is
3
ISL8118
,
As before, when tying VFF to VIN, terms in the previous
equations can be simplified as follows:
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 11 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log graph of Figure 11 by adding the modulator gain, G
(in dB), to the feedback compensation gain, G
is equivalent to multiplying the modulator transfer function and
the compensation transfer function and then plotting the
resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, F
d
----------------------------- -
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
F
F
F
F
MAX
Z1
Z2
P1
P2
V
OSC
0
=
=
=
=
LOG
⋅
V
20
------------------------------ -
2π R
-------------------------------------------------
2π
------------------------------ -
2π R
-------------------------------------------- -
2π R
IN
log
⋅
⋅
⋅
⋅
(
=
1
R
⎛
⎝
1
2
2
3
R2
------- -
R1
-------------------------- -
0.16 V
1
⋅
⋅
⋅
1
1
+
1 V
C
C
-------------------- -
C
⎞
⎠
C
1
R
⋅
1
3
1
3
⋅
+
⋅
F
IN
) C
C
C
Z1
⋅
IN
2
F
2
F
P2
LC
3
Z2
=
against the capabilities of the error
SW
6.25
F
F
.
CE
P1
CL
F
0
, is constructed on the log-
F
20
P2
log
G
CL
COMPENSATION GAIN
d
---------------------------------
OPEN LOOP E/A GAIN
CLOSED LOOP GAIN
MAX V
G
V
MODULATOR GAIN
MOD
OSC
FB
FREQUENCY
⋅
(in dB). This
IN
April 7, 2009
G
(EQ. 18)
(EQ. 19)
(EQ. 20)
(EQ. 22)
(EQ. 21)
FB
MOD
FN6325.1