IR3521MTRPBF International Rectifier, IR3521MTRPBF Datasheet - Page 18

• Manufacturer Part Number: IR3521MTRPBF
• Description: IC CTRL XPHASE3 SVID 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3521MTRPBF

• Applications: Processor
• Current - Supply: 10mA
• Voltage - Supply: 4.75 V ~ 7.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: *
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output 1 (VDD) Adaptive Voltage Positioning (continued)
The voltage difference between VDRP1 and FB1 represents the gained up average current information. Placing a
resistor R
current forced onto the FB1 pin. This current, which can be calculated using (VDRP1-VDAC1) / R
offset voltage produced across R
VDAC1 reference voltage, the output regulation voltage will be varied. When the load current increases, the
adaptive positioning voltage V(VDRP1) increases accordingly. (VDRP1-VDAC1) / R
across the feedback resistor R
positioning voltage can be programmed by the resistor R
converter output impedance. The offset and slope of the converter output impedance are referenced to VDAC1 and
are not affected by changes in the VDAC1 voltage.
Output1 Inductor DCR Temperature Compensation
A negative temperature coefficient (NTC) thermistor can be used for output1 inductor DCR temperature
compensation. The thermistor should be placed close to the output1 inductors and connected in parallel with the
feedback resistor, as shown in Figure 10. The resistor in series with the thermistor is used to reduce the nonlinearity
of the thermistor.
Remote Voltage Sensing
VOSEN
differential amplifiers are high speed, have low input offset and low input bias currents to ensure accurate voltage
sensing and fast transient response.
Start-up Sequence
The IR3521 has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DEL
and hiccup mode timing. Constant current sources and sinks control the charge and discharge rates of the
SS/DEL
Figure 11 depicts the SVID start-up sequence. If the ENABLE input is asserted and there are no faults, the SS/DEL
pin will begin charging, the pre-PWROK 2 bit Boot VID codes are read and stored, and both VDAC pins transition to
the pre-PWROK Boot VID code. The error amplifier output EAOUT
The error amplifier will then regulate the converter’s output voltage to match the V(SS/DEL
converter output reaches the 2-bit Boot VID code. The SS/DEL
the threshold of Delay Comparator where the PGOOD output is allowed to go high. The SVID interface is activated
upon PWROK assertion and the VDAC
SVID commands.
VCCL under voltage, over current, or a low signal on the ENABLE input immediately sets the fault latch, which
causes the EAOUT pin to drive low, thereby turning off the phase IC drivers. The PGOOD pin also drives low and
SS/DEL
comparator allowing another soft start charge cycle to occur.
Other fault conditions, such as output over voltage, open VOSNS sense lines, or an open phase timing daisy chain
set a different group of fault latches that can only be reset by cycling VCCL power. These faults discharge
SS/DEL
SVID OFF codes turn off the converter by discharging SS/DEL
low. Upon receipt of a non-off SVID code the converter will re-soft start and transition to the voltage represented by
the SVID code as shown in Figure 11.
The converter can be disabled by pulling the SS/DELx pins below 0.6V.
X
X
X
X
+ and VOSEN
.
, pull down EAOUT
DRP1
discharges to 0.2V. If the fault has cleared, the fault latch will be reset by the SS/DEL
between VDRP1 and FB1 converts the gained up current information (in the form of a voltage) into a
X
- are used for remote sensing and connected directly to the load. The remote sense
X
and drive PGOOD low.
FB1
FB1
, and makes the output voltage lower proportional to the load current. The
. Since the error amplifier will force the loop to maintain FB1 to equal the
X
X
along with the converter output voltage will change in response to any
and LGND pins controls soft start timing, over-current protection delay
Page 18
DRP1
X
so that the droop impedance produces the desired
and pulling down EAOUTx but do not drive PGOOD
X
voltage continues to increase until it rises above
X
is clamped low until SS/DEL
DRP1
increases the voltage drop
X
)-1.4V offset until the
IR3521
DRP1
X
V3.03
reaches 1.4V.
,
will vary the
X
discharge
X