IR3521MTRPBF International Rectifier, IR3521MTRPBF Datasheet
IR3521MTRPBF
Specifications of IR3521MTRPBF
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IR3521MTRPBF Summary of contents
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... Detection and protection of open remote sense lines Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO Small thermally enhanced 32L MLPQ (5mm x 5mm) package ORDERING INFORMATION Device IR3521MTRPBF IR3521MPBF (Samples Only) TM XPHASE3 TM Phase IC provides a full featured and flexible way to 2 ...
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APPLICATION CIRCUIT 12V Q3 RVCCLDRV PGOOD SVC SVD 1 SVD PWROK 2 PWROK ENABLE 3 ENABLE 4 IIN2 CSS/DEL2 5 SS/DEL2 CVDAC2 RVDAC2 6 VDAC2 ROCSET2 7 OCSET2 8 EAOUT2 RCP2 CCP21 RFB22 CCP22 RFB21 CVCCL9 RVCCLFB1 RVCCLFB2 EPAD 24 ...
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PIN DESCRIPTION PIN# PIN SYMBOL 1 SVD SVD (Serial VID Data bidirectional signal that is an input and open drain output for both master (AMD processor) and slave (IR3521), requires an external bias voltage and should not be ...
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PIN# PIN SYMBOL 20 SS/DEL1 Programs output 1 startup and over current protection delay timing. Connect an external capacitor to LGND to program. 21 IIN1 Output 1 average current input from the output 1 phase IC(s). This pin is also ...
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ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of ...
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RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN-x ≤ 0.3V, 0 ELECTRICAL CHARACTERISTICS The electrical characteristics table shows the spread of values guaranteed within the recommended operating conditions (unless otherwise specified). Typical ...
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PARAMETER Soft Start and Delay Start Delay Measure Enable to EAOUTx activation Start-up Time Measure Enable activation to PGOOD OC Delay Time V(IINx) – V(OCSETx) = 500 mV SS/DELx to FBx Input Offset With FBx = 0V, adjust V(SS/DELx) until ...
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PARAMETER Under Voltage Threshold - Voutx Increasing Under Voltage Threshold Hysteresis Output Voltage Leakage Current VCCL Activation Threshold Over Voltage Protection (OVP) Comparators Threshold at Power-up Voutx Threshold Voltage OVP Release Voltage during Normal Operation Threshold during Dynamic VID down ...
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PHSOUT FREQUENCY VS RROSC CHART 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 5 10 Figure 2 - Phout Frequency vs. RROSC chart Response Open Open Open Daisy Sense Voltage Latch UV & ...
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SYSTEM SET POINT TEST The converter output voltage is determined by the system set point voltage which is the voltage that appears at the FBx pins when the converter is in regulation. The set point voltage includes error terms for ...
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SYSTEM THEORY OF OPERATION PWM Control Method The PWM block diagram of the xPHASE3 with trailing edge modulation is used to provide system control. A voltage type error amplifier with high-gain and wide-bandwidth, located in the Control IC, is used ...
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Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 ...
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PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The ...
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Figure 7 Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled ...
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IR3521 THEORY OF OPERATION Block Diagram The Block diagram of the IR3521 is shown in Figure 8. The following discussions are applicable to either output plane unless otherwise specified. Serial VID Control The two Serial VID Interface (SVID) pins SVC ...
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POR VDD SELECT MODE D Q VCCLDRV VCCL-UVLO VCCL REGULATOR . Q AMPLIFIER VCCLFB + OV1-2 DISABLE - 1.2V 0.94 0.86 + VCCL UVLO - VCCL UVL COMPARATOR SELECT MODE DISABLE VCCL UVLO OC2 AFTER VRRDY OC2 Bf VRRDY UV ...
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Control IC VDAC1 VDAC1 Error Amplifier + EAOUT1 - RFB1 FB1 IFB VDRP RDRP1 Amplifier VDRP1 - IIN1 + VOUT1 Remote Sense VOSEN1+ + Amplifier VOSEN1- - Figure 9 Adaptive voltage positioning Control IC IFB Remote Sense Amplifier Figure 10 ...
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Output 1 (VDD) Adaptive Voltage Positioning (continued) The voltage difference between VDRP1 and FB1 represents the gained up average current information. Placing a resistor R between VDRP1 and FB1 converts the gained up current information (in the form of a ...
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VCC (12V) ENABLE 2-Bit Boot VID 2-Bit Boot SVC READ & STORE VID On-Hold 2-Bit Boot VID 2-Bit Boot SVD READ & STORE VID On-Hold 2-Bit Boot VID Voltage VDACx 0.8V 4.0V 3.92V 1.4V SS/DEL EAOUT VOUT PGOOD PWROK START ...
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Serial VID Interface Protocol and VID-on-the-fly Transition The IR3521 supports the AMD SVI bus protocol and the AMD Server and desktop SVI wire protocol which are 2 based on High-Speed I C. SVID commands from an AMD processor are communicated ...
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Table 3 - AMD 7 BIT SVID CODES SVID [6:0] Voltage (V) 000_0000 1.5500 000_0001 1.5375 000_0010 1.5250 000_0011 1.5125 000_0100 1.5000 000_0101 1.4875 000_0110 1.4750 000_0111 1.4625 000_1000 1.4500 000_1001 1.4375 000_1010 1.4250 000_1011 1.4125 000_1100 1.4000 000_1101 1.3875 ...
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Over-Current Hiccup Protection after Soft Start The over current limit threshold is set by a resistor connected between OCSET the hiccup over-current protection with delay after PGOOD is asserted. The delay is required since over-current conditions can occur as part ...
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Figure 14 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz VCCL Under Voltage Lockout (UVLO) The IR3521 does not directly monitor VCC for under voltage lockout but instead monitors the system VCCL supply voltage since this voltage ...
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Open Voltage Loop Detection The output voltage range of error amplifier is continuously monitored to ensure the voltage loop is in regulation. If any fault condition forces the error amplifier output above VCCL-1.08V for 8 PHSOUT switching cycles, the fault ...
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OUTPUT OVP VOLTAGE THRESHOLD (Vout) VCCL-800 mV IIN (PHASE IC ISHARE) GATEH (PHASE IC) GATEL (PHASE IC) FAULT LATCH ERROR AMPLIFIER VDAC OUTPUT (EAOUT) NORMAL OPERATION Figure 15 - Over-voltage protection during normal operation VID VDAC OV THRESHOLD OUTPUT VOLTAGE ...
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Open Remote Sense Line Protection If either remote sense line VOSEN The IR3521 continuously monitors the VOUT are applied to the VOSEN + and VOSEN X higher than 90% of V(VCCL) will be present at VOSEN be high. If VOSEN ...
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APPLICATIONS INFORMATION Q4 12V RVCCLFB1 RVCCLFB2 RVCCLDRV VDAC2 VDDPWRGD SVC EPAD SVD 1 24 SVD PSI_L ROSC PWROK 2 23 PWROK ROSC RDRP11 3 22 ENABLE ENABLE VDRP1 RDRP12 IR3521 4 21 IIN2 IIN1 CSS/DEL2 CONTROL CSS/DEL1 5 20 SS/DEL2 ...
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DESIGN PROCEDURES - IR3521 AND IR3508 CHIPSET IR3521 EXTERNAL COMPONENTS All the output components are selected using one output but suitable for both unless otherwise specified. Oscillator Resistor R osc R The IR3521 generates square wave pulses to synchronize the ...
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Over Current Setting Resistor R The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from (7), ...
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Adaptive voltage positioning lowers the converter voltage by R the converter. Pre-select feedback resistor R R DRP Calculate the desired effective feedback resistor at the maximum temperature negative temperature constant (NTC) thermistor R ...
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IDD Dynamic OC Limit Capacitor The latest AMD processors require two over current limits: one for normal thermal design current (TDC) operation and the other for system IDD_Spike. TDC over-current is set by following instructions outlined in the Over Current ...
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When a step load is applied, the capacitor acts as a short-circuit, at that instant, and pushes the OCSET signal up by ∆V (i.e. change in IIN) instantaneously. After an increase in its level, the OCP signal starts decaying exponentially ...
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IR3508 EXTERNAL COMPONENTS Inductor Current Sensing Capacitor C The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor parallel with the inductor are chosen to match the time constant of the ...
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VOLTAGE LOOP COMPENSATION The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop introduces extra zero ...
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Type III Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Assume the RC, resistor and capacitor across the output inductors, and L/DCR time constant matches, the crossover frequency and phase margin of the voltage ...
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K C FB CURRENT SHARE LOOP COMPENSATION The internal compensation of current share loop ensures that crossover frequency of the current share ...
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DESIGN EXAMPLE – AMD FIVE + ONE PHASE DUAL OUTPUT CONVERTER (FIGURE 17) SPECIFICATIONS Input Voltage DAC Voltage: V =1.2 V DAC No Load Output Voltage Offset for output1: V Output1 Current: I =95 ADC O1 ...
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VDAC Slew Rate Programming Capacitor C SINK C 14 VDAC DOWN R ...
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577 ROOM CS DRP the case of thermal compensation is required, use equation (14) to (17) to select the R IR3508 ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. Dedicate at least one middle layer for a ground plane LGND. ...
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PCB METAL AND COMPONENT PLACEMENT Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to prevent shorting. Lead land length should be equal to maximum part ...
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SOLDER RESIST The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
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STENCIL DESIGN The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 32L MLPQ ( Body) θ o =24.4 C/W, θ =0. Page 44 IR3521 o C/W V3.03 ...
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This product has been designed and qualified for the Consumer market. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Data and specifications subject to change without notice. Qualification Standards can be found on IR’s ...