MCZ33976EG Freescale Semiconductor, MCZ33976EG Datasheet - Page 16

• Manufacturer Part Number: MCZ33976EG
• Description: IC DRIVER DUAL GAUGE SPI 24-SOIC
• Manufacturer: Freescale Semiconductor
• Type: Serial Peripheral Interface (SPI) Dual Step Motor Gauge Driverr

Specifications of MCZ33976EG

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 2
• Current - Output: 100mA
• Voltage - Supply: 6.5 V ~ 26 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Supply Current: 4 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

changed by command. Velocities can range from position 1
(00000001) to position 225 (11111111).
Addresses 010 and 011 — Gauge 0/1 Position Registers
(POS0R, POS1R)
Address 011 (Gauge 1 Position Register) Register bits PO
11: PO0 are written to when communicating the desired
pointer positions.
Table 9. Gauge 0 Position Register (POS0R)
The bits in
(i.e., hold counts) for Gauge 0 (1 = Damping disabled;
0 = Damping enabled).
.
Table 10. Gauge 1 Position Register (POS1R)
The bits in
(i.e., hold counts) for Gauge 1 (1 = Damping disabled;
0 = Damping enabled).
Gauge 1. Pointer positions can range from 0
(000000000000) to position 4095 (111111111111). For a
step motor requiring 12 microsteps per degree of pointer
movement, the maximum pointer sweep is 341.25°
(4095 ÷ 12).
Address 100 — Gauge Return to Zero Register (RTZR)
page 17) is written to return the gauge pointers to the zero
position. During an RTZ event, the pointer is returned to zero
using full steps, where only one coil is driven at any point in
time. The back electromotive force (EMF) signal present on
16
33976
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Read
Read
Write
Write
Bits
Bits
SI Address 010 (Gauge 0 Position Register) and SI
HE0 12 (D12) — This bit is used to disable the damping
HE1 12 (D12) — This bit is used to disable the damping
P1 11:P1 0 (D11:D0) — Desired pointer position of
Gauge Return to Zero Register (RTZR) (refer to
HE012
HE112
Table 9
Table 10
D12
D12
–
–
are write-only.
are write-only.
P0 11
P1 11
D11
D11
–
–
P0 10
P1 10
D10
D10
–
–
P0 9
P1 9
D9
D9
–
–
P0 8
P1 8
D8
D8
–
–
Table
P0 7
P1 7
D7
D7
11,
–
–
Address 010
Address 011
P0 6
P1 6
D6
D6
bit is used to disable the damping (i.e., hold counts) for each
respective gauge. This feature allows the user to easily turn
on and off the damping that was configured with the
RMPSELR. Disabling the hold counts allows the pointer to
decelerate to the commanded position, as fast as possible
down the velocity ramp. When disabled, the acceleration and
deceleration of the pointer are symmetrical.
–
Gauge 0. Pointer positions can range from 0
(000000000000) to position 4095 (111111111111). For a
step motor requiring 12 microsteps per degree of pointer
movement, the maximum pointer sweep is 341.25°.
–
the non-driven coil is integrated and its results are stored in
an accumulator.
Gauge 0 if RZ0 is logic [0], and Gauge 1 if RZ0 is logic [1],
respectively. Similarly, a logic [0] written to bit RZ1 disables a
Return to Zero for Gauge 0 when RZ0 is logic [0], and
Gauge 1 when RZ0 is logic [1], respectively.
commands.
logic [0] results in a typical RTZ event, automatically
providing a Stop when a stall condition is detected. A logic [1]
will result in RTZ movement, causing a Stop if a logic [0] is
written to bit RZ0. This feature is useful during development
and characterization of RTZ requirements.
Commanded positions can range from 0 to 4095. The D12
P0 11:P0 0 (D11:D0) — Desired pointer position of
A logic [1] written to bit RZ1 enables a Return to Zero for
Bits D12:D5 and D3:D2 must be at logic [0] for valid RTZR
Bit RZ4 is used to enable an unconditional RTZ event. A
P0 5
P1 5
D5
D5
–
–
P0 4
P1 4
D4
D4
–
–
Analog Integrated Circuit Device Data
P0 3
P1 3
D3
D3
–
–
Freescale Semiconductor
P1 2
P02
D2
D2
–
–
P1 1
P01
D1
D1
–
–
P0 0
P1 0
D0
D0
–
–