DP8421ATVX-25 National Semiconductor, DP8421ATVX-25 Datasheet - Page 5

• Manufacturer Part Number: DP8421ATVX-25
• Description: IC CTRLR/DVR CMOS PROGRAM 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8421ATVX-25

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8421ATVX-25

2 1 ADDRESS R W AND PROGRAMMING SIGNALS
2 2 DRAM CONTROL SIGNALS
R0 –10
R0 –9
C0 –10
C0 –9
B0 B1
ECAS0–3
WIN
COLINC
(EXTNDRF)
ML
Q0–10
Q0 –9
Q0 –8
RAS0–3
CAS0–3
WE
(RFRQ)
2 0 Signal Descriptions
Name
Pin
Applicable to All)
DP8422A
DP8420A 21A
DP8422A
DP8420A 21A
DP8422A
DP8421A
DP8421A
Device (If not
Output
Input
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
ROW ADDRESS These inputs are used to specify the row address during an access
to the DRAM They are also used to program the chip when ML is asserted (except
R10)
COLUMN ADDRESS These inputs are used to specify the column address during an
access to the DRAM They are also used to program the chip when ML is asserted
(except C10)
BANK SELECT Depending on programming these inputs are used to select a group
of RAS and CAS outputs to assert during an access They are also used to program
the chip when ML is asserted
ENABLE CAS These inputs are used to enable a single or group of CAS outputs
when asserted In combination with the B0 B1 and the programming bits these
inputs select which CAS output or CAS outputs will assert during an access The
ECAS signals can also be used to toggle a group of CAS outputs for page nibble
mode accesses They also can be used for byte write operations If ECAS0 is
negated during programming continuing to assert the ECAS0 while negating AREQ
or AREQB during an access will cause the CAS outputs to be extended while the
RAS outputs are negated (the ECASn inputs have no effect during scrubbing
refreshes)
WRITE ENABLE IN This input is used to signify a write operation to the DRAM If
ECAS0 is asserted during programming the WE output will follow this input This
input asserted will also cause CAS to delay to the next positive clock edge if address
bit C9 is asserted during programming
COLUMN INCREMENT When the address latches are used and RFIP is negated
this input functions as COLINC Asserting this signal causes the column address to
be incremented by one When RFIP is asserted this signal is used to extend the
refresh cycle by any number of periods of CLK until it is negated
MODE LOAD This input signal when low enables the internal programming register
that stores the programming information
DRAM ADDRESS These outputs are the multiplexed output of the R0– 9 10 and
C0–9 10 and form the DRAM address bus These outputs contain the refresh
address whenever RFIP is asserted They contain high capacitive drivers with 20
series damping resistors
ROW ADDRESS STROBES These outputs are asserted to latch the row address
contained on the outputs Q0 – 8 9 10 into the DRAM When RFIP is asserted the
RAS outputs are used to latch the refresh row address contained on the Q0– 8 9 10
outputs in the DRAM These outputs contain high capacitive drivers with 20
damping resistors
COLUMN ADDRESS STROBES These outputs are asserted to latch the column
address contained on the outputs Q0– 8 9 10 into the DRAM These outputs have
high capacitive drivers with 20
WRITE ENABLE or REFRESH REQUEST This output asserted specifies a write
operation to the DRAM When negated this output specifies a read operation to the
DRAM When the DP8420A 21A 22A is programmed in address pipelining mode or
when ECAS0 is negated during programming this output will function as RFRQ
When asserted this pin specifies that 13 s or 15 s have passed If DISRFSH is
negated the DP8420A 21A 22A will perform an internal refresh as soon as possible
If DISRFRSH is asserted RFRQ can be used to externally request a refresh through
the input RFSH This output has a high capacitive driver and a 20
resistor
5
series damping resistors
Description
series damping
series