DP8421ATVX-25 National Semiconductor, DP8421ATVX-25 Datasheet - Page 26

• Manufacturer Part Number: DP8421ATVX-25
• Description: IC CTRLR/DVR CMOS PROGRAM 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8421ATVX-25

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8421ATVX-25

5 0 Refresh Options
5 2 3 Error Scrubbing during Refresh
The DP8420A 21A 22A support error scrubbing during all
RAS DRAM refreshes Error scrubbing during refresh is se-
lected through bits C4–C6 with bit R9 negated during pro-
gramming Error scrubbing can not be used with staggered
refresh (see Section 8 0) Error scrubbing during refresh al-
lows a CAS or group of CASs to assert during the all RAS
refresh as shown in Figure 18 This allows data to be read
from the DRAM array and passed through an Error Detec-
tion And Correction Chip EDAC If the EDAC determines
that the data contains a single bit error and corrects that
error the refresh cycle can be extended with the input ex-
(Continued)
FIGURE 18 Error Scrubbing during Refresh
26
tend refresh EXTNDRF and a read-modify-write operation
can be performed by asserting WE It is the responsibility of
the designer to ensure that WE is negated The DP8422A
has a 24-bit internal refresh address counter that contains
the 11 row 11 column and 2 bank addresses The
DP8420A 21A have a 22-bit internal refresh address coun-
ter that contains the 10 row 10 column and 2 bank address-
es These counters are configured as bank column row
with the row address as the least significant bits The bank
counter bits are then used with the programming selection
to determine which CAS or group of CASs will assert during
a refresh
TL F 8588– 46