CY14B101L-SZ45XCT Cypress Semiconductor Corp, CY14B101L-SZ45XCT Datasheet - Page 4

• Manufacturer Part Number: CY14B101L-SZ45XCT
• Description: IC NVSRAM 1MBIT 45NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14B101L-SZ45XCT

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-SOIC (7.5mm Width)
• Word Size: 8b
• Organization: 128Kx8
• Density: 1Mb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 50mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Operation
The CY14B101L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B101L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The CY14B101L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
When the READ is initiated by an address transition, the outputs
are valid after a delay of t
initiated by CE or OE, the outputs are valid at t
whichever is later (READ cycle 2). The data outputs repeatedly
respond to address changes within the t
the need for transitions on any control input pins, and remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle.
The data on the common IO pins DQ
memory if it has valid t
WRITE or before the end of an CE controlled WRITE. Keep OE
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE is left LOW, internal circuitry turns off
the output buffers t
AutoStore Operation
The CY14B101L stores data to nvSRAM using one of three
storage operations:
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101L.
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
Document Number: 001-06400 Rev. *K
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
0–16
determines the 131,072 data bytes accessed.
HZWE
CC
SD
after WE goes LOW.
, before the end of a WE controlled
AA
pin drops below V
(READ cycle 1). If the READ is
CAP
pin from V
0–7
AA
CAP
access time without
are written into the
SWITCH
pin. This stored
ACE
CC
CAP
. A STORE
or at t
, the part
capacitor.
CC
DOE
to
,
Figure 2
(V
Characteristics
the V
A pull up is placed on WE to hold it inactive during power up.
Figure 2. AutoStore Mode
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B101L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B101L conditionally initiates a STORE operation
after t
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin should be exter-
nally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B101L continues SRAM operations for t
t
is in progress when HSB is pulled LOW, it allows a time, t
to complete. However, any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
If HSB is not used, it is left unconnected.
DELAY
CAP
CAP
DELAY
) for automatic store operation. Refer to the
, multiple SRAM READ operations take place. If a WRITE
shows the proper connection of the storage capacitor
pin is driven to 5V by a charge pump internal to the chip.
. An actual STORE cycle only begins if a WRITE to
on page 8 for the size of V
V
CAP
V
WE
CC
CAP
CY14B101L
. The voltage on
DELAY
DC Electrical
Page 4 of 20
V
CC
. During
DELAY
HSB.
[+] Feedback