CY14B101L-SZ45XCT Cypress Semiconductor Corp, CY14B101L-SZ45XCT Datasheet - Page 3

• Manufacturer Part Number: CY14B101L-SZ45XCT
• Description: IC NVSRAM 1MBIT 45NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14B101L-SZ45XCT

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-SOIC (7.5mm Width)
• Word Size: 8b
• Organization: 128Kx8
• Density: 1Mb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 50mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pinouts
Table 1. Pin Definitions
Document Number: 001-06400 Rev. *K
Pin Name
DQ
A
V
HSB
0
V
V
WE
CE
OE
NC
0
–A
CAP
SS
CC
-DQ
16
7
Alt
W
E
G
V
DQ
DQ
DQ
A
A
A
No Connect
CAP
V
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
A
A
A
A
A
A
A
A
Power Supply Power Supply Inputs to the Device.
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
16
14
12
SS
7
6
5
4
3
2
1
0
0
1
2
I/O Type
Ground
Input
Input
Input
Input
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
to nonvolatile elements.
No Connect. This pin is not connected to the die.
18
32
31
30
29
28
27
26
25
24
23
22
21
20
19
17
V
A
HSB
WE
A
A
A
A
OE
A
CE
DQ
DQ
DQ
DQ
DQ
CC
15
13
8
9
11
10
7
6
5
4
3
Description
V
DQ2
V
DQ0
DQ1
CAP
NC
NC
NC
NC
NC
NC
NC
NC
A
A
A
A
SS
A
A
A
A
A
A
A
16
14
12
4
1
0
6
5
3
2
7
13
14
16
17
18
19
1
2
3
4
5
6
7
8
9
10
11
12
15
20
21
22
23
24
(not to scale)
Top View
CY14B101L
48
47
46
43
42
41
40
39
37
36
35
34
33
32
29
28
27
26
45
44
38
31
30
25
V
HSB
NC
NC
NC
NC
A
WE
DQ6
OE
NC
NC
V
A
CE
DQ5
DQ4
Page 3 of 20
A
A
A
DQ3
V
A
DQ7
CC
15
SS
13
8
11
10
CC
9
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