CY7C1382C-167AC Cypress Semiconductor Corp, CY7C1382C-167AC Datasheet - Page 8

• Manufacturer Part Number: CY7C1382C-167AC
• Description: IC SRAM 18MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1382C-167AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1543

Document #: 38-05237 Rev. *D
CY7C1380C–Pin Definitions
Name
V
V
MODE
TDO
TDI
TMS
TCK
NC
SSQ
DDQ
5,10,21,26,55,
4,11,20,27,54,
14,16,66,
60,71,
61,70,
TQFP
39,38
76
77
31
-
-
-
-
A1,F1,J1,M1,
A7,F7,J7,M7,
R1,T1,T2,J3,
L4,J5,R5,6T,
B1,C1,
B7,C7,
BGA
(continued)
U1,
D4,
6U,
U7
R3
U5
U3
U2
U4
R7
-
E3,E9,F3,F9,G
N2,N5,N7,N10
,P1,A1,B11,P2
A11,B1,C2,C1
C3,C9,D3,D9,
L9,M3,M9,N3,
0,H1,H3,H9,
G9,J3,J9,
K3,K9,L3,
,R2,N6
fBGA
H10,
N9
R1
P7
P5
R5
R7
3,
-
Synchronous
Synchronous
Synchronous
JTAG-Clock
JTAG serial
JTAG serial
JTAG serial
I/O Ground
I/O Power
Supply
output
Input-
Static
input
input
I/O
-
Ground for the I/O circuitry.
Power supply for the I/O circuitry.
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to V
or left floating selects interleaved burst
sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an
internal pull-up.
Serial data-out to the JTAG circuit. Delivers
data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be
disconnected. This pin is not available on TQFP
packages.
Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be discon-
nected or connected to V
available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be discon-
nected or connected to V
available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to V
TQFP packages.
No Connects. Not internally connected to the
die
SS
Description
. This pin is not available on
DD
DD
CY7C1380C
CY7C1382C
. This pin is not
. This pin is not
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DD