CY7C1382C-167AC Cypress Semiconductor Corp, CY7C1382C-167AC Datasheet - Page 13

• Manufacturer Part Number: CY7C1382C-167AC
• Description: IC SRAM 18MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1382C-167AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1543

Document #: 38-05237 Rev. *D
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Address Table
(MODE = Floating or V
ZZ Mode Electrical Characteristics
Truth Table
Linear Burst Address Table
(MODE = GND)
I
t
t
t
t
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Snooze Mode,Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
DDZZ
ZZS
ZZREC
ZZI
RZZI
Address
Address
Parameter
A1: A0
A1: A0
First
First
00
01
10
00
01
10
11
11
Operation
[ 3, 4, 5, 6, 7, 8]
Address
Address
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Second
Second
A1: A0
A1: A0
01
00
11
10
01
10
11
00
DD
)
Add. Used
Address
Address
Description
External
External
External
External
External
A1: A0
A1: A0
Third
Third
None
None
None
None
None
None
Next
Next
Next
10
00
01
10
00
01
11
11
CE
H
X
X
X
H
L
L
L
L
L
L
L
L
L
Address
Address
1
Fourth
A1: A0
Fourth
A1: A0
11
10
01
00
11
00
01
10
CE
H
H
H
H
H
X
X
X
X
L
X
L
X
X
2
CE
X
X
H
X
H
X
X
X
X
L
L
L
L
L
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
3
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW
.
ZZ ADSP
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Test Conditions
DD
DD
– 0.2V
– 0.2V
X
H
H
X
H
H
H
H
H
X
L
L
L
L
ADSC
X
X
X
X
X
H
H
H
L
L
L
L
L
L
1
, CE
ADV WRITE OE CLK
X
X
X
X
X
X
X
X
X
X
X
L
L
L
2
, CE
2t
Min.
CYC
0
H
H
H
H
H
X
X
X
X
X
X
X
X
3
L
, ADSP, and ADSC must
ZZREC
CY7C1380C
CY7C1382C
60mA
2t
2t
H
H
H
X
X
X
X
X
X
X
L
L
Max.
L
L
CYC
CYC
after the ZZ input
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H
L-H Tri-State
L-H
L-H Tri-State
L-H
Page 13 of 36
X
Tri-State
Unit
mA
ns
ns
ns
ns
DQ
Q
Q
Q
D
Q