CY14B101K-SP35XI Cypress Semiconductor Corp, CY14B101K-SP35XI Datasheet - Page 14

• Manufacturer Part Number: CY14B101K-SP35XI
• Description: IC NVSRAM 1MBIT 35NS 48SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14B101K-SP35XI

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-SSOP
• Word Size: 8b
• Organization: 128Kx8
• Density: 1Mb
• Interface Type: Parallel
• Access Time (max): 35ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SSOP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: -40C to 85C
• Pin Count: 48
• Mounting: Surface Mount
• Supply Current: 60mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Register Map Detail (continued)
Document Number: 001-06401 Rev. *J
Calibration
Calibration These five bits control the calibration of the clock.
0X1FFF8
0x1FFF7
0x1FFF6
0x1FFF5
OSCEN
WDW
WDS
WDT
PFIE
Sign
WIE
AIE
H/L
P/L
M
0
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator
saves battery or capacitor power during storage.
Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit
is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0.
Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value (D5–D0). This allows
the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to 0 allows bits D5–D0 to be
written to the watchdog register when the next write cycle is complete. This function is explained in detail in the
Timer”
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a
multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of
3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was set
to 0 on a previous cycle.
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin and
the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the alarm
match only affects the AF flag.
Power Fail Enable. When set to 1, the alarm match drives the INT pin and the PF flag. When set to 0, the power fail
monitor affects only the PF flag.
Reserved for future use
High/Low. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW.
Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately
200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L) until the flags register is read.
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1 causes the match circuit
to ignore the date value.
OSCEN
WDS
WIE
D7
D7
D7
D7
M
on page 9.
WDW
AIE
D6
D6
D6
D6
0
0
Calibration
PFIE
Sign
D5
D5
D5
D5
10s Alarm Date
Interrupt Status/Control
Calibration/Control
WatchDog Timer
D4
D4
D4
D4
0
Alarm - Day
H/L
D3
D3
D3
D3
WDT
Calibration
P/L
D2
D2
D2
D2
Alarm Date
D1
D1
D1
D1
0
CY14B101K
Page 14 of 29
“Watchdog
D0
D0
D0
D0
0
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