CY14B101L-SZ45XC Cypress Semiconductor Corp, CY14B101L-SZ45XC Datasheet - Page 11
![IC NVSRAM 1MBIT 45NS 32SOIC](/photos/7/24/72405/428-32-soic_sml.jpg)
CY14B101L-SZ45XC
Manufacturer Part Number
CY14B101L-SZ45XC
Description
IC NVSRAM 1MBIT 45NS 32SOIC
Manufacturer
Cypress Semiconductor Corp
Type
NVSRAMr
Specifications of CY14B101L-SZ45XC
Memory Size
1M (128K x 8)
Package / Case
32-SOIC (7.5mm Width)
Interface
Parallel
Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Speed
45ns
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
45ns
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
32
Operating Temperature Range
0°C To +70°C
Word Size
8b
Organization
128Kx8
Density
1Mb
Interface Type
Parallel
Access Time (max)
45ns
Operating Supply Voltage (typ)
3.3V
Package Type
SOIC
Operating Temperature Classification
Commercial
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Pin Count
32
Mounting
Surface Mount
Supply Current
50mA
Memory Configuration
128K X 8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY14B101L-SZ45XC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Switching Waveforms
Notes
Document Number: 001-06400 Rev. *K
SRAM Write Cycle
t
t
t
t
t
t
t
t
t
t
11. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
12. CE or WE must be greater than V
WC
PWE
SCE
SD
HD
AW
SA
HA
HZWE
LZWE
Parameter
Cypress
[9]
[9,11]
ADDRESS
DATA OUT
ADDRESS
DATA OUT
DATA IN
DATA IN
Parameter
WE
CE
CE
WE
t
t
t
t
t
t
t
t
t
t
AVAV
WLWH,
ELWH,
DVWH,
WHDX,
AVWH,
AVWL,
WHAX,
WLQZ
WHQX
t
t
t
t
t
t
t
ELEH
AVEL
AVEH
EHAX
WLEH
DVEH
EHDX
Alt
IH
during address transitions.
Figure 8. SRAM Write Cycle 2: CE and OE Controlled
PREVIOUS DATA
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
t
SA
Figure 7. SRAM Write Cycle 1: WE Controlled
t
SA
Description
HIGH IMPEDANCE
t
t
AW
t
PWE
AW
t
HZWE
t
t
t
SCE
SCE
WC
t
WC
t
t
HIGH IMPEDANCE
PWE
SD
DATA VALID
DATA VALID
Min
t
20
25
20
10
20
SD
0
0
0
3
25 ns
Max
10
[11, 12]
t
HA
t
t
t
HD
HA
[11, 12]
HD
Min
35
25
25
12
25
0
0
0
3
35 ns
t
LZWE
Max
13
Min
45
30
30
15
30
0
0
0
3
CY14B101L
45 ns
Page 11 of 20
Max
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback