CY7C185-20PXC Cypress Semiconductor Corp, CY7C185-20PXC Datasheet - Page 3

• Manufacturer Part Number: CY7C185-20PXC
• Description: IC SRAM 64KBIT 20NS 28DIP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C185-20PXC

• Memory Size: 64K (8K x 8)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 20 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 110 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Memory Configuration: 8K X 8
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 28
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Density: 64Kb
• Access Time (max): 20ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 13b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Supply Current: 110mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 8K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2157-5; CY7C185-20PXC

Switching Characteristics
Document #: 38-05043 Rev. *D
OUTPUT
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE1
ACE2
DOE
LZOE
HZOE
LZCE1
LZCE2
HZCE
PU
PD
WC
SCE1
SCE2
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
5. t
6. At any temperature and voltage condition, t
7. The internal write time of the memory is defined by the overlap of CE
Parameter
I
signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
OL
HZOE,
INCLUDING
5V
/I
OH
JIG AND
SCOPE
t
HZCE
and 30-pF load capacitance.
30 pF
[7]
, and t
(a)
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
CE
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
CE
CE
CE
CE
CE
Write Cycle Time
CE
CE
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
R1 481 
1
2
1
2
1
2
1
2
1
2
1
2
are specified with C
LOW to Power Down
LOW to Data Valid
HIGH to Data Valid
LOW to Low Z
HIGH to Low Z
HIGH to High Z
LOW to High Z
LOW to Power Up
to HIGH to Power Up
HIGH to Power Down
LOW to Write End
HIGH to Write End
R2
255
Description
OUTPUT
Over the Operating Range
HZCE
[6]
[5]
[5]
INCLUDING
L
[5, 6]
5V
= 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage.
JIGAND
Figure 1. AC Test Loads and Waveforms
is less than t
SCOPE
5 pF
(b)
LZCE1
R1 481 
and t
1
LOW, CE
R2
255
LZCE2
[4]
Min
15
15
12
12
12
12
3
3
3
3
0
0
0
8
0
3
for any given device.
2
HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
-15
Max
15
15
15
15
8
7
7
7
GND
3.0V
Equivalent to:
 5 ns
Min
20
20
15
15
15
15
10
OUTPUT
5
3
5
3
0
0
0
0
5
10%
-20
Max
20
20
20
20
9
8
8
7
ALL INPUT PULSES
90%
THÉVENIN EQUIVALENT
167
Min
35
35
20
20
25
20
12
5
3
5
3
0
0
0
0
5
-35
Max
35
35
35
15
10
10
20
8
90%
1.73V
10%
CY7C185
 5 ns
Page 3 of 12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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