CY7C185-35LMB Cypress Semiconductor Corp, CY7C185-35LMB Datasheet

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CY7C185-35LMB

Manufacturer Part Number
CY7C185-35LMB
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C185-35LMB

Lead Free Status / RoHS Status
Not Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C185-35LMB
Manufacturer:
CYP
Quantity:
1 196
1bCY7C185
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *B
Features
Selection Guide
Logic Block Diagram
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Notes:
• High speed
• Fast t
• Low active power
• Low standby power
• CMOS for optimum speed/power
• Easy memory expansion with CE
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in non Pb-free 28-pin (300-Mil) Molded SOJ,
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
— 15 ns
— 715 mW
— 85 mW
28-pin (300-Mil) Molded SOIC and both Pb-free and non
Pb-free in 28-pin (300-Mil) Molded DIP
DOE
CE
CE
WE
OE
1
2
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
1
, CE
COLUMN DECODER
INPUT BUFFER
2
and OE features
ARRAY
8K x 8
198 Champion Court
130
-15
15
15
POWER
DOWN
Functional Description
The CY7C185 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
HIGH chip enable (CE
and tri-state drivers. This device has an automatic
power-down feature (CE
consumption by 70% when deselected. The CY7C185 is in a
standard 300-mil-wide DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
inputs are both LOW and CE
input/output pins (I/O
location addressed by the address present on the address
pins (A
selecting the device and enabling the outputs, CE
active LOW, CE
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
0
through A
110
-20
20
15
San Jose
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
active HIGH, while WE remains inactive or
12
0
1
2
3
4
5
6
7
,
). Reading the device is accomplished by
0
CA 95134-1709
2
through I/O
), and active LOW output enable (OE)
8K x 8 Static RAM
1
2
or CE
100
-25
Pin Configurations
25
15
[1]
is HIGH, data on the eight data
GND
I/O
I/O
I/O
A
A
A
NC
Revised July 24, 2006
A
A
A
A
A
A 9
10
11
12
7
4
5
6
7
8
0
1
2
) is written into the memory
2
DIP/SOJ
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
), reducing the power
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CY7C185
408-943-2600
V
WE
CE
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
3
2
1
0
1
100
), an active
2
1
7
6
5
4
3
-35
35
15
1
1
and WE
and OE
[+] Feedback

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CY7C185-35LMB Summary of contents

Page 1

... LOW chip enable (CE HIGH chip enable (CE and tri-state drivers. This device has an automatic power-down feature (CE consumption by 70% when deselected. The CY7C185 standard 300-mil-wide DIP, SOJ, or SOIC package. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE ...

Page 2

... V –5 +5 –5 CC ≤ –5 +5 –5 CC 130 , 40 ≤ – 0.3V, – 0.3V or Test Conditions T = 25° MHz 5.0V CC CY7C185 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° 5V ± 10% – +85 C –20 –25, -35 Max. Min. Max. Unit 2.4 V 0.4 0 0.3V 2 ...

Page 3

... HZCE LZCE1 LZCE2 LOW, CE HIGH, and WE LOW. All 3 signals must be active to initiate a write and either 1 2 CY7C185 ALL INPUT PULSES 90% 90% 10% 10% ≤ THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V -25 -35 Min. Max. Min. Max. ...

Page 4

... DATA VALID 50 LOW, CE HIGH and WE LOW going HIGH or CE going LOW. The data input set-up and hold timing should be referenced to the 1 2 CY7C185 DATA VALID t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB and WE must be LOW and CE must be HIGH 1 2 Page [+] Feedback ...

Page 5

... During this period, the I/Os are in the output state and input signals should not be applied. 13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t Document #: 38-05043 Rev SCEI SCE2 t PWE t SD DATA VALID SCE1 SCE2 DATA VALID IN and t HZWE CY7C185 Page [+] Feedback ...

Page 6

... Switching Waveforms (continued) Write Cycle No. 3(WE Controlled, OE LOW) ADDRESS DATA I/O NOTE 12 t HZWE Note: 14 goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state Document #: 38-05043 Rev. *B [11,12,13,14 SCE1 t SCE2 DATA VALID IN CY7C185 LZWE Page [+] Feedback ...

Page 7

... TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4. =25°C A 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) CY7C185 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 V =5. =25° 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs ...

Page 8

... Ordering Information Speed (ns) Ordering Code 15 CY7C185-15VC CY7C185-15VI 20 CY7C185-20PC CY7C185-20PXC CY7C185-20VC 25 CY7C185-25PC CY7C185-25VC 35 CY7C185-35PC CY7C185-35SC Document #: 38-05043 Rev Input/Output X High Z Deselect/Power-Down X High Z Deselect/Power-Down L Data Out Read X Data In Write H High Z Deselect Package Name Package Type 51-85031 28-pin (300-Mil) Molded SOJ 28-pin (300-Mil) Molded SOJ ...

Page 9

... SEATING PLANE 1.345[34.16] 1.385[35.18] 0.120[3.05] 0.140[3.55] 0.015[0.38] 0.060[1.52] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] SEE LEAD END OPTION LEAD END OPTION CY7C185 DIMENSIONS IN INCHES [MM] MIN. MAX. REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 0.290[7.36] 0.325[8.25] 0.009[0.23] 3° MIN. 0.012[0.30] 0.310[7.87] 0.385[9.78] 51-85014-*D Page ...

Page 10

... MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 4. PACKAGE WEIGHT 0.85gms * 0.394[10.01] 0.419[10.64] 0.026[0.66] 0.032[0.81] SEATING PLANE 0.092[2.33] 0.105[2.67] 0.004[0.10] * CY7C185 MIN. MAX. PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG. 0.0091[0.23] 0.015[0.38] 0.0125[3.17] 0.050[1.27] 51-85026-*D Page ...

Page 11

... Cypress against all charges. 28-pin (300-Mil) Molded SOJ (51-85031) PIN 0.291 0.330 0.300 0.350 28 SEATING PLANE 0.120 0.140 0.004 0.025 MIN. CY7C185 A DETAIL EXTERNAL LEAD DESIGN 0.026 0.032 0.013 0.014 0.019 0.020 OPTION 1 OPTION 2 0.007 0.013 ...

Page 12

... Document History Page Document Title: CY7C185 Static RAM Document Number: 38-05043 Issue Orig. of REV. ECN NO. Date Change ** 107145 09/10/01 *A 116470 09/16/02 *B 486744 See ECN Document #: 38-05043 Rev. *B Description of Change SZV Change from Spec number: 38-00037 to 38-05043 CEA Add applications foot note to data sheet ...

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