5173N24-U THAT, 5173N24-U Datasheet - Page 14

• Manufacturer Part Number: 5173N24-U
• Description: Microphone Preamplifiers 36V, 100mA
• Manufacturer: THAT

Specifications of 5173N24-U

• Rohs: yes
• Common Mode Rejection Ratio (min): - 9 dB
• Input Offset Voltage: - 1.75 mV to + 1.75 mV
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN-24
• Input Voltage Range (max): 3.6 V, 17 V
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V, 4.75 V to 17 V
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 2 uA, 7.6 mA
• Supply Voltage - Max: 3.6 V, 17 V
• Supply Voltage - Min: 3 V, 4.75 V
• Thd Plus Noise: 0.001 %
• Voltage Gain Db: 60 dB

Document 600166 Rev 01
and C
not affect common-mode rejection.
Power Supply Decoupling
of the 1570, the servo in the 5173, and to minimize
digital switching noise from propagating on the
power supplies. The V
nected to the same analog supply which powers the
analog gain stage, while the V
in common with other logic circuitry (microproces-
sors, etc.) in the unit.
(C
pins 12 (D
the digital output driver bus.
directly under the 5173. Note that the part includes
back-to-back diodes limiting the maximum voltage
difference between these nodes. If even on a transient
basis (e.g., supply spikes) a voltage difference of over
0.5 V exists between A
will flow which may damage the part.
supply voltages never exceed the absolute maximum
ratings even under transient conditions.
integrated differential servo is required for proper
operation of the system as shown in the application
schematics. By using the servo amplifier in feedback,
output offset can be controlled over a wide range of
gains.
ommends that C
the size of C
contributing noise to the preamplifier, we recom-
mend that the servo’s output be divided down by
approximately 1000:1 by the combination of R
and R
Reset (RST pin)
isters to their default state (see Parameter defini-
tions register definitions in SPI Port section for
default values after reset). This pin is typically con-
nected to system reset or to a port on the host micro-
controller.
enabled or disabled for the GAIN and GPO
Zero Crossing Detector (and TRC pin)
16
Power supply decoupling is required for stability
THAT recommends one decoupling capacitor
A
Care should be taken to ensure that the power
As described above (in the Theory section), the
In order to optimize settling behavior, THAT rec-
Asserting the RST pin low forces all internal reg-
The integrated zero-crossing detector may be
) for the digital power supply, placed close to
GND
8
8
/R
affect only differential signals, and thus do
2
and D
.
GND
4
) and 11 (V
and C
GND
12
and C
5
. As well, to avoid the servo from
should be connected together
CC
GND
Tel: [phone]; Fax: [phone]; Web: www.thatcorp.com
and V
DD
13
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
), as these pins connect to
be approximately one-half
and D
DD
Copyright © 2012, THAT Corporation; All rights reserved.
EE
pin may be powered
pins should be con-
GND
, large currents
7
/R
Page 14 of 20
1
parameters independently (see Table 5). When
enabled, it prevents gain and/or GPO changes from
occurring until the differential output signal wave-
form is within ±12.5 mV of zero.
logic low (Table 5), Gain and GPO updates are made
immediately following a rising edge on the /CS pin.
When GAINMODE and GPOMODE are logic high,
updates are made on the next output signal zero-
crossing after a rising edge on the /CS pin.
detector may unacceptably delay a gain or GPO
change from taking place. A timeout, set by R
C
R
crossing time-out function operates as follows:
crossing” mode depends on the application. Immedi-
ate mode has the advantage of providing gain
updates with short deterministic latency, whereas
zero crossing mode has the advantage of minimizing
glitches and zipper noise.
Busy (BSY pin)
gain setting is not equal to the value in the GAIN reg-
ister, i.e. when a gain update is pending a zero-
crossing. This pin may be monitored by the host
microcontroller (e.g. connected to an external inter-
rupt pin) in order to hold off a new gain command
until the previous gain command has been executed.
external processing (typically a DSP) the BUSY sig-
nal can be employed to synchronize the external gain
changes with those implemented by the 5173 (most
importantly, when the interpolated gain “wraps” from
maximum to minimum as each 5173 3dB step
occurs). Note that latency in A/D conversion must be
considered when attempting to synchronize digital
with analog gain updates.
T
T
, is provided to force a change to occur within
C
When the GAINMODE or GPOMODE bits are
When no signal is present, the zero-crossing
The
The BSY pin is asserted high when the current
If finer gain steps (e.g. 1dB) are implemented in
T
A) C
beginning of an SPI command sequence), and is
allowed to start charging when /CS goes high
(the end of an SPI command sequence).
B) Gain and/or GPOs are updated on the next
zero-crossing or when the voltage on the TRC
pin charges to 0.7*V
first.
The recommended time constant for R
~22mS (e.g. C
mS if a zero crossing is not detected. The zero-
T
choice
is discharged when /CS goes low (the
Audio Preamplifier Digital Controller IC
between
T
= 1nF and R
DD
-- whichever event occurs
“immediate”
T
= 22MΩ ).
THAT5173
vs
T
T
C
“zero
T
and
is