72V2113L7-5BC IDT, 72V2113L7-5BC Datasheet - Page 34

• Manufacturer Part Number: 72V2113L7-5BC
• Description: FIFO 256Kx18 /512Kx9 3.3V SUPERSYNC II FIFO
• Manufacturer: IDT

Specifications of 72V2113L7-5BC

• Data Bus Width: 18 bit
• Bus Direction: Unidirectional
• Memory Size: 4 Mbit
• Timing Type: Synchronous
• Organization: 256 K x 18
• Maximum Clock Frequency: 133.3 MHz
• Access Time: 7 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 8 V
• Maximum Operating Current: 35 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: BGA-100
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Part # Aliases: IDT72V2113L7-5BC

NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
WCLK
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
RCLK
WCLK
RCLK
WEN
edge of WCLK and the rising edge of RCLK is less than t
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the DT72V2113. If both x9 Input and x9 Output bus Widths are
WEN
REN
REN
SKEW2
PAF
PAE
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
ENS
n words in FIFO
n+1 words in FIFO
t
CLKL
D ⎯ (m + 1) words in FIFO
t
ENH
t
SKEW2
(2)
1
,
(3)
(4)
t
PAES
SKEW2
t
CLKH
, then the PAE deassertion may be delayed one extra RCLK cycle.
2
TM
NARROW BUS FIFO
t
ENS
t
CLKL
TM
NARROW BUS FIFO
34
t
ENS
t
t
PAFA
ENH
n+1 words in FIFO
n+2 words in FIFO
t
ENS
t
ENH
D ⎯ m words
in FIFO
(2)
(3)
,
t
PAFA
1
COMMERCIAL AND INDUSTRIAL
t
PAES
PAES
TEMPERATURE RANGES
). If the time between the rising
2
words in FIFO
D ⎯ (m + 1)
n words in FIFO
n+1 words in FIFO
JUNE 1, 2010
6119 drw22
6119 drw23
(2)
,
(3)